Patents by Inventor Hironobu FURUHASHI

Hironobu FURUHASHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10985210
    Abstract: A nonvolatile storage device includes first and second interconnections and a memory cell between the first and second interconnections. The memory cell includes a storage element, a first switch, and a second switch. The first switch has two terminals and transitions from an off-state to an on-state when a first threshold voltage is applied between its terminals and then voltage between the terminals falls to a first hold voltage. The second switch has two terminals and transitions from an off-state to an on-state when a second threshold voltage is applied between its terminals and then voltage between the terminals falls to a second hold voltage. An off-current of the first switch is less than an off-current of the second switch. The first threshold voltage is greater than the second threshold voltage, which is greater than the first hold voltage, which is greater than or equal to the second hold voltage.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: April 20, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masahiko Nakayama, Toshihiko Nagase, Tomomi Funayama, Hironobu Furuhashi, Kazumasa Sunouchi
  • Publication number: 20210074355
    Abstract: A semiconductor memory device includes: first wirings; second wirings intersecting the first wirings; and memory cells. Each of the memory cells is respectively formed between one of the first wirings and one of the second wirings. In a set operation, a set pulse is supplied between one of the first wirings and one of the second wirings. In a reset operation, a reset pulse is supplied between one of the first wirings and one of the second wirings. In a first operation, a first pulse is supplied between one of the first wirings and one of the second wirings. the first pulse has an amplitude equal to or greater than the greater of an amplitude of the set pulse and an amplitude of the reset pulse and has a pulse width greater than a pulse width of the set pulse.
    Type: Application
    Filed: March 3, 2020
    Publication date: March 11, 2021
    Applicant: KIOXIA CORPORATION
    Inventors: Takayuki TSUKAMOTO, Hironobu FURUHASHI, Takeshi SUGIMOTO, Masanori KOMURA
  • Patent number: 10943632
    Abstract: A magnetic storage device includes a memory cell with a magnetoresistive effect element and a switching element connected in series. The magnetoresistive effect element is configured to change from a first resistance state to a second resistance state that is lower in resistance than the first resistance state in response to a first write operation flowing current in a first direction through the memory cell and to change from the second resistance state to the first resistance state in response to a second write operation flowing current in a second direction through the memory cell. The switching element has a first voltage drop associated with current flows in the first direction and has a second voltage drop associated with current flows the second direction that is lower than the first voltage drop.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hironobu Furuhashi
  • Publication number: 20200303455
    Abstract: A nonvolatile storage device includes first and second interconnections and a memory cell between the first and second interconnections. The memory cell includes a storage element, a first switch, and a second switch. The first switch has two terminals and transitions from an off-state to an on-state when a first threshold voltage is applied between its terminals and then voltage between the terminals falls to a first hold voltage. The second switch has two terminals and transitions from an off-state to an on-state when a second threshold voltage is applied between its terminals and then voltage between the terminals falls to a second hold voltage. An off-current of the first switch is less than an off-current of the second switch. The first threshold voltage is greater than the second threshold voltage, which is greater than the first hold voltage, which is greater than or equal to the second hold voltage.
    Type: Application
    Filed: September 3, 2019
    Publication date: September 24, 2020
    Inventors: Masahiko NAKAYAMA, Toshihiko NAGASE, Tomomi FUNAYAMA, Hironobu FURUHASHI, Kazumasa SUNOUCHI
  • Publication number: 20200303454
    Abstract: A magnetic storage device includes a memory cell with a magnetoresistive effect element and a switching element connected in series. The magnetoresistive effect element is configured to change from a first resistance state to a second resistance state that is lower in resistance than the first resistance state in response to a first write operation flowing current in a first direction through the memory cell and to change from the second resistance state to the first resistance state in response to a second write operation flowing current in a second direction through the memory cell. The switching element has a first voltage drop associated with current flows in the first direction and has a second voltage drop associated with current flows the second direction that is lower than the first voltage drop.
    Type: Application
    Filed: September 3, 2019
    Publication date: September 24, 2020
    Inventor: Hironobu FURUHASHI
  • Patent number: 10770509
    Abstract: According to one embodiment, a magnetic device includes a first memory cell including a magnetoresistive effect element, a selector, and a first barrier material disposed between the selector and the magnetoresistive effect element, wherein the first barrier material has a thermal conductivity of 5 W/mK or lower.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: September 8, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hironobu Furuhashi
  • Publication number: 20200274063
    Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, and a first chalcogen layer provided therebetween. A third conductive layer and a fourth conductive layer have a second chalcogen layer provided therebetween. The second chalcogen layer contains tellurium (Te). When a minimum value and a maximum value of a composition ratio of tellurium in the second chalcogen layer observed along the first direction are a first minimum value and a first maximum value, respectively, the first minimum value is observed at a position closer to the third conductive layer than a center position in the first direction of the second chalcogen layer, and the first maximum value is observed at a position closer to the fourth conductive layer than the center position in the first direction of the second chalcogen layer.
    Type: Application
    Filed: August 26, 2019
    Publication date: August 27, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Hironobu Furuhashi
  • Publication number: 20190288032
    Abstract: According to one embodiment, a magnetic device includes a first memory cell including a magnetoresistive effect element, a selector, and a first barrier material disposed between the selector and the magnetoresistive effect element, wherein the first barrier material has a thermal conductivity of 5 W/mK or lower.
    Type: Application
    Filed: September 5, 2018
    Publication date: September 19, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Hironobu FURUHASHI
  • Patent number: 9672887
    Abstract: According to one embodiment, a semiconductor memory includes a first memory cell stably storing data after a first time from an end of a write operation, a buffer latching the data in the write operation, and a control circuit controlling a first read operation when the first read operation is executed right after the write operation for the first memory cell is executed, where the first read operation is an operation for the first memory cell, and the first read operation is an operation reading the data from the buffer without accessing the first memory cell.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: June 6, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hironobu Furuhashi, Masahiko Nakayama, Katsuhiko Hoya
  • Publication number: 20170069366
    Abstract: According to one embodiment, a semiconductor memory includes a first memory cell stably storing data after a first time from an end of a write operation, a buffer latching the data in the write operation, and a control circuit controlling a first read operation when the first read operation is executed right after the write operation for the first memory cell is executed, where the first read operation is an operation for the first memory cell, and the first read operation is an operation reading the data from the buffer without accessing the first memory cell.
    Type: Application
    Filed: March 10, 2016
    Publication date: March 9, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hironobu FURUHASHI, Masahiko NAKAYAMA, Katsuhiko HOYA
  • Publication number: 20160268500
    Abstract: According to one embodiment, a resistance change memory includes first and second semiconductor pillars on a conductive region, a first word line including a first portion surrounding a side surface of the first pillar, a second portion surrounding a side surface of the second pillar, and a third portion connecting between the first and second portions, the first and second portions being physically separated from one another, a first resistance change element connected to an upper portion of the first semiconductor pillar, and a second resistance change element connected to an upper portion of the second semiconductor pillar.
    Type: Application
    Filed: August 26, 2015
    Publication date: September 15, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hironobu FURUHASHI, Kenji AOYAMA
  • Patent number: 9384829
    Abstract: A memory device includes n (n being an integer of 2 or more) resistance change films being series connected to each other. Each of the resistance change films is a superlattice film in which plural pairs of a first crystal layer made of a first compound and a second crystal layer made of a second compound are alternately stacked. An average composition of the entire resistance change film or an arrangement pitch of the first crystal layers and the second crystal layers are mutually different among the n resistance change films.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: July 5, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hironobu Furuhashi, Iwao Kunishima, Susumu Shuto, Yoshiaki Asao, Gaku Sudo
  • Publication number: 20140185359
    Abstract: According to one embodiment, a memory device includes n (n being an integer of 2 or more) resistance change films being series connected to each other. Each of the resistance change films is a superlattice film in which a plurality of pairs of a first crystal layer made of a first compound and a second crystal layer made of a second compound are alternately stacked. Average composition of the entire resistance change film or arrangement pitch of the first crystal layers and the second crystal layers are mutually different among the n resistance change films.
    Type: Application
    Filed: March 20, 2013
    Publication date: July 3, 2014
    Inventors: Hironobu FURUHASHI, Iwao KUNISHIMA, Susumu SHUTO, Yoshiaki ASAO, Gaku SUDO
  • Patent number: 8753973
    Abstract: According to one embodiment, a method of fabricating a semiconductor memory device includes patterning a first memory cell layer and a first interconnect layer to form a first structure of a linear pattern in a first region and a second structure in a second region, forming a second interconnect layer and a second memory cell layer, and patterning the second memory cell layer and the second interconnect layer to form, in the first region, a third structure having a linear pattern and having a folded pattern immediately on the second structure. The method further includes removing the second memory cell layer and the second interconnect layer in the folded pattern, and the first memory cell layer of the second structure positioned under the folded pattern.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: June 17, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hironobu Furuhashi
  • Publication number: 20130237028
    Abstract: According to one embodiment, a method of fabricating a semiconductor memory device includes patterning a first memory cell layer and a first interconnect layer to form a first structure of a linear pattern in a first region and a second structure in a second region, forming a second interconnect layer and a second memory cell layer, and patterning the second memory cell layer and the second interconnect layer to form, in the first region, a third structure having a linear pattern and having a folded pattern immediately on the second structure. The method further includes removing the second memory cell layer and the second interconnect layer in the folded pattern, and the first memory cell layer of the second structure positioned under the folded pattern.
    Type: Application
    Filed: September 5, 2012
    Publication date: September 12, 2013
    Inventor: Hironobu FURUHASHI
  • Publication number: 20100165757
    Abstract: A semiconductor memory device includes a semiconductor layer; a source layer and a drain layer in the semiconductor layer; an electrically floating body region in the semiconductor layer between the source layer and the drain layer, accumulating or discharging charges for storing logical data; a gate dielectric film on the body region; and a first gate electrode and a second gate electrode on one body region via the gate dielectric film, the first and the second gate electrodes separated from each other in a channel length direction of a memory cell comprising the drain layer, the source layer, and the body region.
    Type: Application
    Filed: September 18, 2009
    Publication date: July 1, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hironobu FURUHASHI
  • Publication number: 20100133613
    Abstract: A semiconductor memory device includes a supporting substrate; an insulation film provided on the supporting substrate; a source layer provided on the insulation film; a drain layer provided on the insulation film; a body region provided between the source layer and the drain layer and being in an electrically floating state, the body region accumulating electric charges or discharging electric charges in order to store data; a boundary gate dielectric film provided at least on a boundary portion between the body region and the source layer and on a boundary portion between the body region and the drain layer; and a center gate dielectric film provided adjacently to the boundary gate dielectric film on the body region, the center gate dielectric film having more interface states than the boundary gate dielectric film has.
    Type: Application
    Filed: September 22, 2009
    Publication date: June 3, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hironobu FURUHASHI