Patents by Inventor Hironobu Miyamoto

Hironobu Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200298914
    Abstract: A vehicle underbody structure includes a catalyst disposed in a front portion of an exhaust pipe; a cover member for covering the catalyst from above; and a heat insulator disposed inside a tunnel portion behind the catalyst and configured to cover the exhaust pipe from above. The heat insulator is disposed away from the tunnel portion by a predetermined gap in an up-down direction. A front portion of the heat insulator and a rear portion of the cover member are disposed in such a way as to overlap each other. A front end of the heat insulator is disposed on the upper side with respect to a rear end of the cover member.
    Type: Application
    Filed: August 21, 2018
    Publication date: September 24, 2020
    Applicant: MAZDA MOTOR CORPORATION
    Inventors: Hironobu SAKASHITA, Masaru CHIKITA, Kazuhiro KAGEYAMA, Kohei MIYAMOTO
  • Publication number: 20200161445
    Abstract: An n-type epitaxial layer is formed on an n-type semiconductor substrate made of silicon carbide. p-type body regions are formed in the epitaxial layer, and n-type source region is formed in the body region. On the body region between the source region and the epitaxial layer, a gate electrode is formed via a gate dielectric film, and an interlayer insulating film having an opening is formed so as to cover the gate electrode. A source electrode electrically connected to the source region and the body regions is formed in the opening. A recombination layer is formed between the body region and a basal plane dislocation is a layer having point defect density higher than that of the epitaxial layer located directly under the recombination layer or having a metal added to the epitaxial layer.
    Type: Application
    Filed: October 9, 2019
    Publication date: May 21, 2020
    Inventors: Hironobu MIYAMOTO, Yasuhiro OKAMOTO, Kenichi HISADA, Koichi ARAI, Nobuo MACHIDA
  • Patent number: 10461159
    Abstract: Characteristics of a semiconductor device using a nitride semiconductor are improved. A semiconductor device of the present invention includes a buffer layer, a channel layer, a barrier layer, a mesa-type 2DEG dissolving layer, a source electrode, a drain electrode, a gate insulating film formed on the mesa-type 2DEG dissolving layer, and an overlying gate electrode. The gate insulating film of the semiconductor device includes a sputtered film formed on the mesa-type 2DEG dissolving layer and a CVD film formed on the sputtered film. The sputtered film is formed in a non-oxidizing atmosphere by a sputtering process using a target including an insulator. This makes it possible to reduce positive charge amount at a MOS interface and in gate insulating film and increase a threshold voltage, and thus improve normally-off characteristics.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 29, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hironobu Miyamoto, Tatsuo Nakayawa, Yasuhiro Okamoto, Atsushi Tsuboi
  • Publication number: 20190288105
    Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.
    Type: Application
    Filed: February 22, 2019
    Publication date: September 19, 2019
    Inventors: Kenichi HISADA, Koichi ARAI, Hironobu MIYAMOTO
  • Patent number: 10410868
    Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap wider than a band gap of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, a gate electrode placed in the trench over a gate insulating film, and a first electrode and a second electrode formed over the second nitride semiconductor layer on both sides of the gate electrode, respectively.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: September 10, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
  • Patent number: 10388779
    Abstract: A semiconductor device includes a codoped layer, a channel layer, a barrier layer, and a gate electrode disposed in a trench extending through the barrier layer and reaching a middle point in the channel layer via a gate insulating film. On both sides of the gate electrode, a source electrode and a drain electrode are formed. On the source electrode side, an n-type semiconductor region is disposed to fix a potential and achieve a charge removing effect while, on the drain electrode side, a p-type semiconductor region is disposed to improve a drain breakdown voltage. By introducing hydrogen into a region of the codoped layer containing Mg as a p-type impurity in an amount larger than that of Si as an n-type impurity where the n-type semiconductor region is to be formed, it is possible to inactivate Mg and provide the n-type semiconductor region.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: August 20, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto
  • Publication number: 20190233939
    Abstract: A transparent conductive film includes a crystalline transparent conductive layer obtained by forming an amorphous transparent conductive layer on a polymeric film substrate by sputtering, and crystallizing the amorphous transparent conductive layer. Defining that the amorphous transparent conductive layer has a carrier density represented by na×1019 and Hall mobility represented by ?a, that the crystalline transparent conductive layer has a carrier density represented by nc×1019 and Hall mobility represented by ?c, and that a length of motion L is represented by {(nc?na)2+(?c??a)}1/2, the amorphous transparent conductive layer before the crystallizing process has a carrier density na×1019 of (10?60)×1019/cm3 and Hall mobility ?a of 10-25 cm2/V·s, and the crystalline transparent conductive layer after the crystallizing process has a carrier density nc×1019 of (80?150)×1019/cm3 and Hall mobility ?c of 20-40 cm2/V·s, and the length of motion L is 50-150.
    Type: Application
    Filed: April 9, 2019
    Publication date: August 1, 2019
    Applicant: NITTO DENKO CORPORATION
    Inventors: Kodai Miyamoto, Kazuaki Sasa, Hironobu Machinaga, Eri Ueda, Manami Kurose, Tomotake Nashiki
  • Publication number: 20190237577
    Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.
    Type: Application
    Filed: December 18, 2018
    Publication date: August 1, 2019
    Inventors: Yasuhiro OKAMOTO, Nobuo MACHIDA, Koichi ARAI, Kenichi HISADA, Yasunori YAMASHITA, Satoshi EGUCHI, Hironobu MIYAMOTO, Atsushi SAKAI, Katsumi EIKYU
  • Patent number: 10249715
    Abstract: Properties of a semiconductor device are improved. A semiconductor device is configured so as to include a voltage clamp layer, a channel underlayer, a channel layer, and a barrier layer, which are formed in order above a substrate, a trench that extends up to the middle of the channel layer while penetrating through the barrier layer, a gate electrode disposed within the trench with a gate insulating film in between, a source electrode and a drain electrode formed above the barrier layer on both sides of the gate electrode, and a fourth electrode electrically coupled to the voltage clamp layer. The fourth electrode is electrically isolated from the source electrode, and a voltage applied to the fourth electrode is different from a voltage applied to the source electrode. Consequently, threshold control can be performed. For example, a threshold of a MISFET can be increased.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: April 2, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Hironobu Miyamoto, Tatsuo Nakayama, Atsushi Tsuboi, Yasuhiro Okamoto, Hiroshi Kawaguchi
  • Patent number: 10243070
    Abstract: A property of a semiconductor device (high electron mobility transistor) is improved. A semiconductor device having a buffer layer, a channel layer, an electron supply layer, a mesa type cap layer, a source electrode, a drain electrode and a gate insulating film covering the cap layer, and a gate electrode formed on the gate insulating film, is configured as follows. The cap layer and the gate electrode are separated from each other by the gate insulating film, and side surfaces of the cap layer, the side surfaces being closer to the drain electrode and the source electrode, have tapered shapes. For example, a taper angle (?1) of the side surface of the cap layer (mesa portion) is equal to or larger than 120 degrees. By this configuration, a TDDB life can be effectively improved, and variation in an ON-resistance can be effectively suppressed.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: March 26, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Hironobu Miyamoto, Yasuhiro Okamoto, Hiroshi Kawaguchi, Tatsuo Nakayama
  • Patent number: 10229992
    Abstract: Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes a buffer layer composed of a first nitride semiconductor layer, a channel layer composed of a second nitride semiconductor layer, and a barrier layer composed of a third nitride semiconductor layer, which are sequentially laminated, and a cap layer composed of a fourth nitride semiconductor layer of mesa type, which is formed over the barrier layer. The semiconductor device also includes a source electrode formed on one side of the cap layer, a drain electrode formed on the other side of the cap layer, and a first gate electrode formed over the cap layer. The first gate electrode and the cap layer are Schottky-joined. A Schottky gate electrode (the first gate electrode) is provided over the cap layer in this way, so that when a gate voltage is applied, an electric field is applied to the entire cap layer and a depletion layer spreads. Therefore, it is possible to suppress a gate leakage current.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: March 12, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinao Miura, Hironobu Miyamoto
  • Patent number: 10199476
    Abstract: A mesa portion of a semiconductor device, which includes a channel base layer formed of a first nitride semiconductor layer, a channel layer formed of a second nitride semiconductor layer, a barrier layer formed of a third nitride semiconductor layer, a mesa-type fourth nitride semiconductor layer, a gate insulating film that covers the mesa portion, and a gate electrode formed over the gate insulating film, is used as a co-doped layer. The mesa portion is used as the co-doped layer, so that interface charges generated at an interface between the gate insulating film and the mesa portion can be cancelled by p-type impurity or n-type impurity in the co-doped layer and a threshold potential can be improved. Further, the fourth nitride semiconductor layer is n-type until the gate insulating film is formed, and the fourth nitride semiconductor layer is made neutral or p-type after the gate insulating film is formed.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: February 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto
  • Publication number: 20190019886
    Abstract: A semiconductor device includes a codoped layer, a channel layer, a barrier layer, and a gate electrode disposed in a trench extending through the barrier layer and reaching a middle point in the channel layer via a gate insulating film. On both sides of the gate electrode, a source electrode and a drain electrode are formed. On the source electrode side, an n-type semiconductor region is disposed to fix a potential and achieve a charge removing effect while, on the drain electrode side, a p-type semiconductor region is disposed to improve a drain breakdown voltage. By introducing hydrogen into a region of the codoped layer containing Mg as a p-type impurity in an amount larger than that of Si as an n-type impurity where the n-type semiconductor region is to be formed, it is possible to inactivate Mg and provide the n-type semiconductor region.
    Type: Application
    Filed: September 19, 2018
    Publication date: January 17, 2019
    Inventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO
  • Publication number: 20180342589
    Abstract: Characteristics of a semiconductor device using a nitride semiconductor are improved. A semiconductor device of the present invention includes a buffer layer, a channel layer, a barrier layer, a mesa-type 2DEG dissolving layer, a source electrode, a drain electrode, a gate insulating film formed on the mesa-type 2DEG dissolving layer, and an overlying gate electrode. The gate insulating film of the semiconductor device includes a sputtered film formed on the mesa-type 2DEG dissolving layer and a CVD film formed on the sputtered film. The sputtered film is formed in a non-oxidizing atmosphere by a sputtering process using a target including an insulator. This makes it possible to reduce positive charge amount at a MOS interface and in gate insulating film and increase a threshold voltage, and thus improve normally-off characteristics.
    Type: Application
    Filed: April 30, 2018
    Publication date: November 29, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Hironobu MIYAMOTO, Tatsuo NAKAYAWA, Yasuhiro OKAMOTO, Atsushi TSUBOI
  • Patent number: 10134850
    Abstract: A semiconductor device includes a channel layer formed over a substrate, a barrier layer formed on the channel layer and a gate electrode. A second gate electrode section is formed on the gate electrode via a gate insulating film. It becomes possible to make an apparent threshold voltage applied to the second gate electrode of a MISFET higher than an original threshold voltage applied to the gate electrode for forming a channel under the gate electrode by providing an MIM section configured by the gate electrode, the gate insulating film and the second gate electrode in this way.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: November 20, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinao Miura, Hironobu Miyamoto
  • Patent number: 10134908
    Abstract: A MISFET is formed to include: a co-doped layer that is formed over a substrate and has an n-type semiconductor region and a p-type semiconductor region; and a gate electrode formed over the co-doped layer via a gate insulation film. The co-doped layer contains a larger amount of Mg, a p-type impurity, than that of Si, an n-type impurity. Accordingly, the carriers (electrons) resulting from the n-type impurities (herein, Si) in the co-doped layer are canceled by the carriers (holes) resulting from p-type impurities (herein, Mg), thereby allowing the co-doped layer to serve as the p-type semiconductor region. Mg can be inactivated by introducing hydrogen into, of the co-doped layer, a region where the n-type semiconductor region is to be formed, thereby allowing the region to serve as the n-type semiconductor region. By thus introducing hydrogen into the co-doped layer, the p-type semiconductor region and the n-type semiconductor region can be formed in the same layer.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: November 20, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto
  • Publication number: 20180308968
    Abstract: Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes a buffer layer composed of a first nitride semiconductor layer, a channel layer composed of a second nitride semiconductor layer, and a barrier layer composed of a third nitride semiconductor layer, which are sequentially laminated, and a cap layer composed of a fourth nitride semiconductor layer of mesa type, which is formed over the barrier layer. The semiconductor device also includes a source electrode formed on one side of the cap layer, a drain electrode formed on the other side of the cap layer, and a first gate electrode formed over the cap layer. The first gate electrode and the cap layer are Schottky-joined. A Schottky gate electrode (the first gate electrode) is provided over the cap layer in this way, so that when a gate voltage is applied, an electric field is applied to the entire cap layer and a depletion layer spreads. Therefore, it is possible to suppress a gate leakage current.
    Type: Application
    Filed: February 26, 2018
    Publication date: October 25, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Yoshinao MIURA, Hironobu MIYAMOTO
  • Patent number: 10109730
    Abstract: A semiconductor device includes a codoped layer, a channel layer, a barrier layer, and a gate electrode disposed in a trench extending through the barrier layer and reaching a middle point in the channel layer via a gate insulating film. On both sides of the gate electrode, a source electrode and a drain electrode are formed. On the source electrode side, an n-type semiconductor region is disposed to fix a potential and achieve a charge removing effect while, on the drain electrode side, a p-type semiconductor region is disposed to improve a drain breakdown voltage. By introducing hydrogen into a region of the codoped layer containing Mg as a p-type impurity in an amount larger than that of Si as an n-type impurity where the n-type semiconductor region is to be formed, it is possible to inactivate Mg and provide the n-type semiconductor region.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: October 23, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto
  • Publication number: 20180233590
    Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).
    Type: Application
    Filed: March 16, 2018
    Publication date: August 16, 2018
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
  • Patent number: 10050142
    Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: August 14, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Ichiro Masumoto, Yasuhiro Okamoto, Shinichi Miyake, Hiroshi Kawaguchi