Abstract: A memory circuit 10 includes: a feed-through input terminal 13 for inputting a signal different from a signal to be inputted when reading and writing memory cells; an intermediate buffer circuit 14 provided between regions where the memory cells are arranged, for relaying the signal inputted through the feed-through input terminal 13; and a feed-through output terminal 15 for outputting the signal relayed by the intermediate buffer circuit 14. Connections between the feed-through input terminal 13 and the intermediate buffer circuit 14 and between the intermediate buffer circuit 14 and the feed-through output terminal 15 are established by feed-through wires 16, 17, respectively. The feed-through wires 16, 17 are not connected to either a wire to be used when reading and wiring the memory cells, or the memory cells.

Abstract: A semiconductor memory device capable of accurately simulating a read-out timing of a memory cell and enhancing a production yield is provided. A dummy column selector is placed so as to be connected to dummy bit lines, and a plurality of dummy cells driving the dummy bit lines are placed at positions farthest in a column direction on a memory array from the side where an amplifier circuit is placed. This configuration allows a timing for driving the bit lines by the memory cells that are placed similarly at positions farthest from the amplifier circuit to be simulated accurately, thus enabling the generation of an amplifier startup signal without delay. Furthermore, a plurality of dummy word lines respectively connected to the plurality of dummy columns allow for readily switching from a dummy cell with a defect to a normal dummy cell.

Abstract: A semiconductor memory device capable of accurately simulating a read-out timing of a memory cell and enhancing a production yield is provided. A dummy column selector is placed so as to be connected to dummy bit lines, and a plurality of dummy cells driving the dummy bit lines are placed at positions farthest in a column direction on a memory array from the side where an amplifier circuit is placed. This configuration allows a timing for driving the bit lines by the memory cells that are placed similarly at positions farthest from the amplifier circuit to be simulated accurately, thus enabling the generation of an amplifier startup signal without delay. Furthermore, a plurality of dummy word lines respectively connected to the plurality of dummy columns allow for readily switching from a dummy cell with a defect to a normal dummy cell.

Abstract: A memory array portion, a connection circuit serving as an interface of the memory array portion and a signal wiring connecting the memory array portion to the connection circuit are provided. Mesh wirings comprising first and second wiring layers are provided on the memory array portion. The connection circuit is connected to a plurality of signal lines comprising a third wiring layer provided on the memory array portion, the connection circuit or the signal wiring, through an intermediate wiring comprising the second wiring layer. The region where the intermediate wiring is provide on the memory array portion or on the signal wiring, and the mesh wiring comprising the second wiring layer is not present on the region where the intermediate wiring is provided.

Abstract: A semiconductor memory device comprises a word line drive circuit including a drive transistor, which drives a word line; a circuit for turning the drive transistor OFF right after an output of the word line drive circuit reaches a high level; and a word-line-voltage increasing circuit for increasing a voltage of the word line after the drive transistor turns OFF. The word-line-voltage increasing circuit includes a coupling capacitor one end of which is connected to the word line, and a capacitor drive circuit an output end of which is connected to the other end of the coupling capacitor. The capacitor drive circuit switches its output from a low level to a high level at turn-OFF timing of the drive transistor. The coupling capacitor includes a wiring line running along the word line.

Abstract: A semiconductor memory device capable of enhancing a production yield is provided. A dummy control circuit activates a first dummy column including a plurality of dummy cells placed at a position close to a row decoder in a row direction and a second dummy column including a plurality of dummy cells placed at a position farthest from the row decoder in a row direction with a plurality of memory cells interposed between the first dummy column and the second dummy column, through first and second dummy word lines. A dummy column selector selects either one of a signal on a first dummy bit line connected to the first dummy column and a signal on a second dummy bit line connected to the second dummy column, and outputs the selected signal to an amplifier control circuit. The amplifier control circuit generates an amplifier startup signal with respect to an amplifier circuit based on a signal from the dummy column selector.

Abstract: A memory array portion, a connection circuit serving as an interface of the memory array portion and a signal wiring connecting the memory array portion to the connection circuit are provided. Mesh wirings comprising first and second wiring layers are provided on the memory array portion. The connection circuit is connected to a plurality of signal lines comprising a third wiring layer provided on the memory array portion, the connection circuit or the signal wiring, through an intermediate wiring comprising the second wiring layer. The region where the intermediate wiring is provide on the memory array portion or on the signal wiring, and the mesh wiring comprising the second wiring layer is not present on the region where the intermediate wiring is provided.

Abstract: A semiconductor device includes: a transmitting section; and a receiving section, wherein the transmitting section and the receiving section are connected to each other through a bus, the transmitting section includes an encoding section for encoding data including a plurality of bits to produce bit-position information which indicates a position of at least one bit selected from the plurality of bits included in the data, and an output section for outputting the bit-position information onto the bus, and the receiving section includes an input section for receiving the bit-position information from the bus, and a decoding section for decoding the bit-position information to produce the data.

Abstract: First and second nodes are coupled together by a bus. The first node includes a detecting circuit for detecting the maximum data transfer capability of a connected node, at least two receiving circuits for receiving data from the bus, and a controlling circuit for selecting, based on an output signal from the detecting circuit and for optimizing the configuration of a receiving unit so as to bring the other of the receiving circuits to a stop. The second node includes a transmitting circuit for transmitting data to the bus and a notifying circuit for notifying the first node of its own maximum transfer capability.

Abstract: A first semiconductor integrated circuit is connected to a second semiconductor integrated circuit with a cable. In the first semiconductor integrated circuit, when a power supply voltage becomes less than a set voltage detection level, a voltage-detecting circuit outputs a voltage-detected signal to lower the voltage of the cable and to stop the operation. The second semiconductor integrated circuit detects the decrease in the voltage of the cable to recognize the halt of the operation of the first semiconductor integrated circuit. In the first semiconductor integrated circuit thus configured, in testing the operation under low-voltage conditions in which the power supply voltage is less than the set voltage detection level, the voltage-detecting circuit receives a control signal from an external terminal to stop the operation forcibly.

Abstract: A power-saving network unit, which is connected to a network made up of a plurality of power-saving network units, includes: network monitoring means; network information memory; power-saving mode setting means; peripheral I/O interface; and digital processor. The network monitoring means monitors a topology of the network, or the interconnection relationship among the power-saving network units. Every time the network has been modified, the network monitoring means stores the modified network topology on the network information memory. The power-saving mode setting means receives the network information stored on the network information memory. If the power-saving network unit is a master or relay node in the network, then the power-saving mode setting means locks the peripheral I/O interface and digital processor of the power-saving network unit to the normal operation mode and prohibits these sections from entering the power-saving mode.

Abstract: The present invention provides a semiconductor integrated circuit having area efficiency and repair efficiency improved by sharing a redundant memory macro among a plurality of SRAM macros. Each of the plurality of memory macros 1A1 and 1A2 includes a memory cell array 1A-3 connected to word lines WL1 to WL32 and bit lines and a redundant circuit that replaces a defective bit line of the memory cell array to a normal bit line and a redundant bit line BLA65 and outputs defect information to a redundant signal line RA. The redundant memory macro 2A includes a redundant memory cell array connected to redundant word lines and the redundant bit line, and a first word line connection circuit that connects a word line corresponding to a memory macro to be repaired and disconnects a word line corresponding to a normal memory macro from the redundant word line.

Abstract: A voltage control circuit for implementing, e.g., the CPS function in which a high-accuracy comparison is performed between a high external voltage and a reference voltage. A diode-connected transistor converts the external voltage to a voltage lower than the external voltage in conjunction with an external voltage dropping resistor. A comparator compares the converted voltage with a specified comparison voltage. The size of the transistor is determined such that the ratio of an increment of the converted voltage to an increment of the external voltage is sufficiently high in a comparison region in which the external voltage is close to the reference voltage. A clamping circuit clamps the converted voltage with a specified limit voltage such that the converted voltage does not exceed the withstand voltage of the circuit.

Abstract: A semiconductor memory device includes: a memory block including a plurality of memory cells; and a test pattern generation circuit for generating at least one test pattern for use in testing the memory block. A first bus line for coupling the memory block and the test pattern generation circuit has a larger width than that of a second bus line for coupling the memory block to the exterior of the semiconductor memory device.

Abstract: A network apparatus is provided, which allows another network apparatus to recognize the disconnection with reliability, if a power supply to the network apparatus is interrupted. A control unit operating with a first power supply outputs a first signal, which is level-converted and supplied as a second signal to an intermediate potential supply unit operating with a second power supply. In the intermediate potential supply unit, a switch receives a reset signal as a switch signal and outputs, when the power supply is interrupted, a ground potential to a driver instead of the second signal. As a result, an intermediate potential supplied to a cable is forcibly set to the ground potential.

Abstract: In the circuit for detecting the voltage level of an analog signal, a conversion circuit converts an analog signal to digital signals by comparing the voltage level of the analog signal with a plurality of reference potentials. A filter circuit matches timings of at least either rising edges or falling edges of the digital signals with each other. This prevents malfunction in the voltage level detection.

Abstract: A semiconductor integrated circuit includes receiver, potential sensor and output fixing circuit. The receiver receives a differential signal that has been transmitted through a twisted pair of signal lines, and outputs a signal in accordance with the differential signal. The potential sensor senses a variation in in-phase potential of the differential signal transmitted through the twisted pair. And the output fixing circuit fixes an output of the receiver at a certain value if the variation sensed by the potential sensor is equal to or greater than a predetermined level. In this configuration, once the variation in the in-phase potential of the differential signal has reached the predetermined level, the output of the receiver is fixed at the certain value. Accordingly, even if the receiver operates erroneously due to the in-phase potential variation, the erroneous output of the receiver is not supplied to the next stage like a digital section.

Abstract: Four memory banks (10 to 13), each having a hierarchical word line structure, are provided. If a particular mode for one of the memory banks is specified by a control packet (PKT), a mode recognizer (15) produces the leading edges of change-of-sub-word enable (SEN0-3) and change-of-column enable (CEN-3) signals with the logical level of change-of-main-word enable (MEN0-3) signal fixed. This is done to make activated ones of sub-word and column select lines changeable in each of the memory banks with the same main word line still selected. In this manner, the row access speeds increase for the respective memory banks.

Abstract: A processing unit for carrying out specified data processing operations while performing read/write operations on data in an internal memory is coupled to a memory control unit for performing read/write operations on data in an external memory. Data exchange is carried out between the internal and external memories through the memory control unit. Data requiring a longer processing time or data frequently accessed is mapped into the internal memory in accordance with the data exchange, thereby improving overall memory system performance.

Abstract: The present invention provides a semiconductor integrated circuit system, having one master chip and a plurality of slave chips, for performing data transfer under a control of a predetermined clock. The system includes: a detection section for detecting a change in a state of the semiconductor integrated circuit system and for producing information indicating the detection result, the state including at least one of temperature and source voltage; and at least one clock phase adjustment section for receiving the information and for adjusting a phase of a clock used in transferring data output by the slave chip based on the information.