Patents by Inventor Hironori Aoki

Hironori Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030128326
    Abstract: An image display in which a resistance value of internal wiring for inputting a signal and a power supply to a driving IC COG-packaged on an insulating substrate composing a display panel is reduced without enlarging external size of the display panel, and a method of manufacturing the image display. In internal wiring 8 for inputting a signal and a power supply to a driving IC 4 COG-packaged on a first insulating substrate 1, first layer internal wiring 8a is composed of a first conductive film forming a scanning line, etc., and second layer internal wiring 8b is composed of a second conductive film forming a signal line, etc. Connecting wiring 15 for connecting the first layer internal wiring 8a and the second layer internal wiring 8b is formed simultaneously with formation of a display electrode, and the internal wiring 8 is formed into a multi-layer structure connected electrically parallel.
    Type: Application
    Filed: December 26, 2002
    Publication date: July 10, 2003
    Applicant: KABUSHIKI KAISHA ADVANCED DISPLAY
    Inventors: Takehisa Yamaguchi, Hironori Aoki
  • Publication number: 20030076289
    Abstract: The present invention is directed to a liquid crystal display apparatus including: a timing circuit for operating a shift register within a timing circuit during a vertical blanking period such that a common signal that has been alternated at a cycle of a Single Horizontal period is applied on counter electrodes during the vertical blanking period and such that a storage electrode signal is applied on storage electrodes having a frequency, phase and amplitude identical to those of the common signal.
    Type: Application
    Filed: December 2, 2002
    Publication date: April 24, 2003
    Applicant: ADVANCED DISPLAY INC.
    Inventors: Susumu Tokonami, Susumu Shibata, Hironori Aoki, Shingo Nagano
  • Patent number: 6524949
    Abstract: There is formed on a semiconductor substrate a lamination of a first insulating film of nondoped silicon glass or the like and, on this first insulating film, a second insulating film of boron phosphor silicate glass or the like, with a conductor layer between the two insulating films. A hole is first dry-etched in the second insulating film, leaving the substrate surface covered by the first insulating film. Then the second insulating film is heated to a reflow temperature such that the hole is thermally deformed, flaring as it extends away from the insulating film. Then a second hole is dry-etched in the first insulating film through the first recited hole in the second insulating film, with the consequent exposure of the semiconductor surface. Then a contract electrode is fabricated by filling the first and the second hole with an electroconductive material into direct contact with the substrate surface.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: February 25, 2003
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Shuichi Kaneko, Hironori Aoki, Akio Iwabuchi
  • Patent number: 6525788
    Abstract: The object of the present invention is to provide a TFT array for obtaining a liquid crystal display apparatus of large screen size, of high aperture ratio, and of high precision without degrading the display quality through cross talks or shot blurs. The TFT array of the present invention is a TFT array substrate comprising: a transparent insulating substrate; a plurality of parallel gate electrode lines; a plurality of parallel source electrode lines crossing to the gate electrode lines; a plurality of TFTs located on each crossing point of the gate electrode lines and the source electrode lines; a passivation film formed on the TFTs; a plurality of transparent pixel electrodes formed on said passivation film corresponding to each said TFT and connected to a drain electrode of each said TFT via contact hole; a plurality of floating electrodes which serve as light shielding layer made of a same layer as that of said gate electrode lines formed in a peripheral portion of each said pixel electrode.
    Type: Grant
    Filed: October 14, 1999
    Date of Patent: February 25, 2003
    Assignee: Advanced Display Inc.
    Inventors: Naoki Nakagawa, Hironori Aoki
  • Patent number: 6515646
    Abstract: The present invention is directed to a liquid crystal display apparatus including: a timing circuit for operating a shift register within a timing circuit during a vertical blanking period such that a common signal that has been alternated at a cycle of a Single Horizontal period is applied on counter electrodes during the vertical blanking period and such that a storage electrode signal is applied on storage electrodes having a frequency, phase and amplitude identical to those of the common signal.
    Type: Grant
    Filed: July 15, 1999
    Date of Patent: February 4, 2003
    Assignee: Advanced Display Inc.
    Inventors: Susumu Tokonami, Susumu Shibata, Hironori Aoki, Shingo Nagano
  • Patent number: 6504581
    Abstract: Method for manufacturing a liquid crystal display apparatus including: a TFT array substrate having a plurality of scanning lines formed on a transparent insulating substrate by a metal film, a plurality of data lines formed on or beneath the scanning lines so as to be separated by an insulating film in such a manner as to intersect the scanning lines, switching elements that are formed by a semiconductor layer at respective intersections between the scanning lines and the data lines, and pixel electrodes that are formed by a transparent conductive film and electrically connected to the switching elements; and a counter substrate provided with a liquid crystal interposed between the TFT array substrate and the counter substrate; wherein a divisional exposing method is adopted as a patterning method on the TFT array substrate, so that adjacent exposing areas within a display area of the liquid crystal display apparatus have overlapped portions with each other, and so that a shot layout is defined in such a man
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: January 7, 2003
    Assignee: Advanced Display Inc.
    Inventors: Miyuki Hirosue, Naoki Nakagawa, Hironori Aoki
  • Publication number: 20020175889
    Abstract: The present invention is directed to a liquid crystal display apparatus including: a timing circuit for operating a shift register within a timing circuit during a vertical blanking period such that a common signal that has been alternated at a cycle of a Single Horizontal period is applied on counter electrodes during the vertical blanking period and such that a storage electrode signal is applied on storage electrodes having a frequency, phase and amplitude identical to those of the common signal.
    Type: Application
    Filed: July 15, 1999
    Publication date: November 28, 2002
    Inventors: SUSUMU TOKONAMI, SUSUMU SHIBATA, HIRONORI AOKI, SHINGO NAGANO
  • Publication number: 20020113934
    Abstract: The present invention provides an array substrate in which delay in signal transmission is reduced and provides a display device in which superior display quality is achieved, by using wirings of low resistivity, and moreover, by suppressing increase in wiring resistance caused by contact resistance.
    Type: Application
    Filed: February 14, 2002
    Publication date: August 22, 2002
    Inventor: Hironori Aoki
  • Publication number: 20020102841
    Abstract: There is formed on a semiconductor substrate a lamination of a first insulating film of nondoped silicon glass or the like and, on this first insulating film, a second insulating film of boron phosphor silicate glass or the like, with a conductor layer between the two insulating films. A hole is first dry-etched in the second insulating film, leaving the substrate surface covered by the first insulating film. Then the second insulating film is heated to a reflow temperature such that the hole is thermally deformed, flaring as it extends away from the insulating film. Then a second hole is dry-etched in the first insulating film through the first recited hole in the second insulating film, with the consequent exposure of the semiconductor surface. Then a contract electrode is fabricated by filling the first and the second hole with an electroconductive material into direct contact with the substrate surface.
    Type: Application
    Filed: October 29, 2001
    Publication date: August 1, 2002
    Applicant: Sanken Electric Co., Ltd.
    Inventors: Shuichi Kaneko, Hironori Aoki, Akio Iwabuchi
  • Publication number: 20020018176
    Abstract: The present invention is a thin film transistor array substrate includes: an insulating substrate; a first metallic pattern formed on said insulting substrate; an insulating film provided on said first metallic pattern; a semiconductor pattern provided on said insulating film; and a second metallic pattern provided on said semiconductor pattern; wherein said second metallic pattern is surrounded by said semiconductor pattern.
    Type: Application
    Filed: March 14, 2001
    Publication date: February 14, 2002
    Applicant: ADVANCED DISPLAY INC.
    Inventors: Kazuhiro Kobayashi, Nobuhiro Nakamura, Kazunori Inoue, Takuji Yoshida, Ken Nakashima, Yuichi Masutani, Hironori Aoki
  • Patent number: 5650834
    Abstract: An active-matrix substrate including a transparent insulative substrate, thin film transistors arranged in a matrix pattern on the transparent substrate, pixel electrodes each connected to a drain electrode of each of the thin film transistors, a plurality of gate lines each adapted to supply a signal to a gate electrode of each of the thin film transistors, a plurality of source signal lines intersecting the plurality of gate lines and each adapted to supply a signal to a source electrode of each of the thin film transistors, a shortcircuiting ring for shortcircuiting each of the signal lines at the periphery of the transparent insulative substrate, and a thin film resistor having a resistance of 10 k.OMEGA. to 500 k.OMEGA. provided intermediate between an input terminal of each of the signal lines and the shortcircuiting ring.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: July 22, 1997
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Asahi Glass Company Ltd.
    Inventors: Naoki Nakagawa, Hironori Aoki, Hiroaki Shimaya
  • Patent number: 5424857
    Abstract: A matrix-type display having a TFT substrate provided with at least a pixel electrode and a thin film transistor; and an opposing electrode; wherein a material for changing an optical property is interposed between the TFT substrate and the opposing electrode; a plurality of thin film transistors arrange in a matrix array on a transparent insulative substrate, each of the thin film transistors being provided to each pixel; a gate signal line interconnecting respective gate electrodes of the thin film transistors arrange in a row or column of the matrix array; a source electrode line interconnecting respective source or drain electrodes of thin film transistor arranged in a column or row of the matrix array; a pixel electrode formed of a transparent conductor film and connected to the source or drain electrode of each of the thin film transistors; a capacitor electrode capacitively coupled to the pixel electrode through a dielectric film; a conductor wire interconnecting the respective capacitive electrode of
    Type: Grant
    Filed: June 21, 1994
    Date of Patent: June 13, 1995
    Assignees: Asahi Glass Company Ltd., Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hironori Aoki, Naoki Nakagawa, Tatsuya Nakayama