Patents by Inventor Hironori Uchikawa

Hironori Uchikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210273655
    Abstract: A memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory stores a multidimensional error correction code in which each of a plurality of symbol groups is encoded by both a first component code and a second component code. The memory controller reads the error correction code from the nonvolatile memory, executes a first decoding process using the first component code and the second component code, and when the first decoding process fails, executes a second decoding process on an error symbol group. The second decoding process includes a process of selecting the positions of a plurality of symbols whose values included in the error symbol group are to be inverted according to a decision rule. The decision rule includes a rule for cyclically shifting a position selected for the second decoding process at to decide the position for the second decoding process at the next time.
    Type: Application
    Filed: August 27, 2020
    Publication date: September 2, 2021
    Inventors: Yuta KUMANO, Hironori UCHIKAWA
  • Publication number: 20210264990
    Abstract: A semiconductor memory includes a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels, a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell.
    Type: Application
    Filed: April 29, 2021
    Publication date: August 26, 2021
    Applicant: Kioxia Corporation
    Inventors: Noboru SHIBATA, Hironori UCHIKAWA, Taira SHIBUYA
  • Publication number: 20210266014
    Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
    Type: Application
    Filed: May 11, 2021
    Publication date: August 26, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi KANNO, Hironori UCHIKAWA
  • Patent number: 11038536
    Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: June 15, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi Kanno, Hironori Uchikawa
  • Publication number: 20210165713
    Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
    Type: Application
    Filed: February 12, 2021
    Publication date: June 3, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Masamichi FUJIWARA, Kazumasa YAMAMOTO, Naoaki KOKUBUN, Tatsuro HITOMI, Hironori UCHIKAWA
  • Patent number: 11025281
    Abstract: A memory system includes a nonvolatile memory and a memory controller that encodes first XOR data generated by performing an exclusive OR operation on pieces of user data, wherein a value of each bit of the XOR data is generated by performing an exclusive OR operation on values of bits that are at one of a plurality of bit positions of a piece of user data, generates codewords by encoding the plurality of pieces of user data and the generated XOR data, respectively, and stores the codewords in the nonvolatile memory. The memory controller also performs a read operation by reading the codewords from the nonvolatile memory and decoding them. When the decoding of two or more of the codewords fails, the memory controller generates second XOR data, and corrects the value of one of the bits corresponding to a codeword whose decoding failed, based on the second XOR data.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: June 1, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Naoko Kifune, Hironori Uchikawa
  • Patent number: 11011239
    Abstract: A semiconductor memory according to an embodiment includes first and second memory cells, first and second memory cell arrays, first and second word lines, and controller. The first and second memory cell array include the first and second memory cells, respectively. The first and second word lines are coupled to the first and second memory cells, respectively. Data of six or more bits including a first bit, a second bit, a third bit, a fourth bit, a fifth bit, and a sixth bit is stored with the use of a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 18, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Noboru Shibata, Hironori Uchikawa, Taira Shibuya
  • Publication number: 20210091792
    Abstract: A memory system includes a nonvolatile memory and a memory controller that encodes first XOR data generated by performing an exclusive OR operation on pieces of user data, wherein a value of each bit of the XOR data is generated by performing an exclusive OR operation on values of bits that are at one of a plurality of bit positions of a piece of user data, generates codewords by encoding the plurality of pieces of user data and the generated XOR data, respectively, and stores the codewords in the nonvolatile memory. The memory controller also performs a read operation by reading the codewords from the nonvolatile memory and decoding them. When the decoding of two or more of the codewords fails, the memory controller generates second XOR data, and corrects the value of one of the bits corresponding to a codeword whose decoding failed, based on the second XOR data.
    Type: Application
    Filed: March 2, 2020
    Publication date: March 25, 2021
    Inventors: Naoko KIFUNE, Hironori UCHIKAWA
  • Patent number: 10956264
    Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: March 23, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Masamichi Fujiwara, Kazumasa Yamamoto, Naoaki Kokubun, Tatsuro Hitomi, Hironori Uchikawa
  • Publication number: 20210081275
    Abstract: A memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory has data encoded with an error correction code stored therein. The memory controller reads data from the nonvolatile memory, calculates likelihood information from the read data and an LLR table for calculating the likelihood information, determines a parameter for a decoding process of the read data based on the likelihood information, executes the decoding process based on the determined parameter, and outputs a decoding result obtained by the decoding process.
    Type: Application
    Filed: February 28, 2020
    Publication date: March 18, 2021
    Inventors: Yuta KUMANO, Hironori UCHIKAWA
  • Patent number: 10908994
    Abstract: A memory system in an embodiment includes a nonvolatile memory and a memory controller. The memory stores a multi-dimensional error correction code including at least one symbol that is capable of being protected by at least a first and a second component code. The controller reads the error correction code from the memory, executes hard decision decoding of the first component code with respect to the read error correction code and outputs a first decoding result and index information for calculating likelihood of the first decoding result, executes, when the hard decision decoding fails, soft decision decoding of the second component code by using the first decoding result and the index information and outputs a decoding result as a hard bit, and, executes, when the soft decision decoding fails, the hard decision decoding with respect to the result of the soft decision decoding output.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: February 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Naoko Kifune, Hironori Uchikawa, Takahiro Fujiki, Daiki Watanabe, Daisuke Fujiwara, Kosuke Morinaga
  • Publication number: 20200301777
    Abstract: A memory system in an embodiment includes a nonvolatile memory and a memory controller. The memory stores a multi-dimensional error correction code including at least one symbol that is capable of being protected by at least a first and a second component code. The controller reads the error correction code from the memory, executes hard decision decoding of the first component code with respect to the read error correction code and outputs a first decoding result and index information for calculating likelihood of the first decoding result, executes, when the hard decision decoding fails, soft decision decoding of the second component code by using the first decoding result and the index information and outputs a decoding result as a hard bit, and, executes, when the soft decision decoding fails, the hard decision decoding with respect to the result of the soft decision decoding output.
    Type: Application
    Filed: August 15, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Naoko Kifune, Hironori Uchikawa, Takahiro Fujiki, Daiki Watanabe, Daisuke Fujiwara, Kosuke Morinaga
  • Patent number: 10756764
    Abstract: According to one embodiment, a memory system encodes a plurality of data frames written in the same block in an inter-frame direction and generates first parity data, encodes the first parity data in the inter-frame direction and generates second parity data, generates a plurality of pieces of first frame data by concatenating at least a part of the first or second parity data with each of the plurality of data frames, encodes each of the plurality of pieces of first frame data in an intra-frame direction and generates a plurality of third parity data, and writes a plurality of pieces of second frame data obtained by concatenating each of the plurality of pieces of first frame data and each of the plurality of pieces of third parity data in a plurality of pages in the same block in the non-volatile memory one by one.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: August 25, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hironori Uchikawa, Toshikatsu Hida
  • Publication number: 20200227122
    Abstract: According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Noboru SHIBATA, Hironori UCHIKAWA
  • Publication number: 20200211655
    Abstract: A semiconductor memory according to an embodiment includes first and second memory cells, first and second memory cell arrays, first and second word lines, and controller. The first and second memory cell array include the first and second memory cells, respectively. The first and second word lines are coupled to the first and second memory cells, respectively. Data of six or more bits including a first bit, a second bit, a third bit, a fourth bit, a fifth bit, and a sixth bit is stored with the use of a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.
    Type: Application
    Filed: December 20, 2019
    Publication date: July 2, 2020
    Applicant: KIOXIA CORPORATION
    Inventors: Noboru SHIBATA, Hironori UCHIKAWA, Taira SHIBUYA
  • Patent number: 10613930
    Abstract: In a network storage device that includes a plurality of data storage drives, error correction and/or recovery of data stored on one of the plurality of data storage drives is performed cooperatively by the drive itself and by a storage host that is configured to manage storage in the plurality of data storage drives. When an error-correcting code (ECC) operation performed by the drive cannot correct corrupted data stored on the drive, the storage host can attempt to correct the corrupted data based on parity and user data stored on the remaining data storage drives. In some embodiments, data correction can be performed iteratively between the drive and the storage host. Furthermore, the storage host can control latency associated with error correction by selecting a particular error correction process.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: April 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Hashimoto, Hironori Uchikawa
  • Patent number: 10607707
    Abstract: According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 31, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Noboru Shibata, Hironori Uchikawa
  • Publication number: 20200081774
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a memory controller. Each of first storage regions of each of the nonvolatile memory includes a plurality of second storage regions. Each of pieces of first data includes pieces of second data as storage target data. Third data includes pieces of the second data that are selected one by one from each of the pieces of first data. The memory controller executes first decoding of decoding each of the pieces of first data on the basis of a first error correcting code generated by using the first data, and executes second decoding of decoding the third data including a bit of which reliability, which relates to each bit in each of the second storage regions that fail in the first decoding, is less than reliability of other bits on the basis of a second error correcting code.
    Type: Application
    Filed: March 12, 2019
    Publication date: March 12, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yuta Kumano, Hironori Uchikawa
  • Publication number: 20200081770
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.
    Type: Application
    Filed: November 12, 2019
    Publication date: March 12, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Yuta Kumano, Hironori Uchikawa, Kosuke Morinaga, Naoaki Kokubun, Masahiro Kiyooka, Yoshiki Notani, Kenji Sakurada, Daiki Watanabe
  • Patent number: 10574272
    Abstract: A memory system includes a nonvolatile memory and a memory controller configured to perform reading of a concatenation code from the nonvolatile memory in response to an external command, the memory controller including a decoder circuit which decodes a reception word in the concatenation code. The decoder circuit includes a first external code decoder that performs decoding on an external code portion, an internal code in-error bit estimation unit that performs estimation of an in-error bit on a bit sequence from the first external code decoder, based on a rule for an internal code in the concatenation code, and outputs a set of in-error bits that is obtained by the estimation, and a second external code decoder that performs decoding which uses the set of in-error bits that is output from the internal code in-error bit estimation unit, on the bit sequence from the first external code decoder.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: February 25, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuta Kumano, Kazumasa Yamamoto, Hironori Uchikawa, Akira Yamaga