Patents by Inventor Hiroshi Akahori

Hiroshi Akahori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070275488
    Abstract: A CCD portion 3 is formed on a front surface side of a semiconductor substrate 1. A region of a back surface side of semiconductor substrate 1 that corresponds to CCD portion 3 is thinned while leaving peripheral regions 1a of the region, and an accumulation layer 5 is formed on the back surface side of semiconductor substrate 1. An electrical wiring 7, which is electrically connected to CCD portion 3, and an electrode pad 9, which is electrically connected to electrical wiring 7, are then formed on a region 1b of the front surface side of semiconductor substrate 1 that corresponds to a peripheral region 1a, and a supporting substrate 11 is adhered onto the front surface side of semiconductor substrate 1 so as to cover CCD portion 3 while leaving electrode pad 9 exposed. Semiconductor substrate 1 and supporting substrate 11 are then cut at a thinned portion of semiconductor substrate 1 so as to leave peripheral region 1a corresponding to region 1b at which electrical wiring 7 and electrode pad 9 are formed.
    Type: Application
    Filed: April 14, 2004
    Publication date: November 29, 2007
    Inventors: Hiroya Kobayashi, Hiroshi Akahori, Masaharu Muramatsu
  • Publication number: 20070201275
    Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a second insulating film comprising a plurality of insulating films provided on the charge storage layer and comprising a nitride film as an uppermost layer, and a single-layer control gate electrode provided on the second insulating film and comprising metal silicide.
    Type: Application
    Filed: January 30, 2007
    Publication date: August 30, 2007
    Inventors: Wakako Takeuchi, Hiroshi Akahori, Murato Kawai
  • Publication number: 20070145535
    Abstract: In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.
    Type: Application
    Filed: January 9, 2007
    Publication date: June 28, 2007
    Inventors: Tadahiro Ohmi, Shigetoshi Sugawa, Akinobu Teramoto, Hiroshi Akahori, Keiichi Nii
  • Publication number: 20070063232
    Abstract: An energy ray sensitive region 11 is divided in its horizontal direction into m columns with the vertical direction as the longitudinal direction, divided in its vertical direction into n rows with the horizontal direction as the longitudinal direction, and is thereby provided with m×n photoelectric conversion portions 13 that are arrayed two-dimensionally. Each of these photoelectric conversion portions 13 generates charges in response to the incidence of energy rays. On the front surface side of energy ray sensitive region 11, a plurality of transfer electrodes 15 are disposed so as to cover energy ray sensitive region 11. The plurality of transfer electrodes 15 are respectively disposed with the horizontal direction as the longitudinal direction and are aligned in the vertical direction. The respective transfer electrodes 15 are electrically connected by voltage dividing resistors 17.
    Type: Application
    Filed: April 22, 2004
    Publication date: March 22, 2007
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Hiroshi Akahori, Tatsuki Kasuya
  • Publication number: 20070064134
    Abstract: A solid-state imaging apparatuses IS1 comprises a package P1, a CCD chip 11, chip resistor arrays 21, etc. In package P1, a mounting portion 2, for mounting CCD chip 11 and chip resistor arrays 21, is disposed so as to protrude into a hollow portion 1. Mounting portion 2 has a first planar portion 3 and second planar portions 4, and first planar portion 3and second planar portions 4 are formed to be stepped with respect to each other. CCD chip 11 is mounted and fixed on first planar portion 3via a spacer 13. Chip resistor arrays 21 are mounted and fixed on second planar portions 4. Using the step difference between first planar portion 3 and second planar portions 4, CCD chip 11 and chip resistor arrays 21 are positioned proximally.
    Type: Application
    Filed: April 14, 2004
    Publication date: March 22, 2007
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Hiroya Kobayashi, Hiroshi Akahori, Masaharu Muramatsu
  • Patent number: 7179746
    Abstract: In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: February 20, 2007
    Assignee: Foundation fõr Advancement of Internati{dot over (o)}nal Science
    Inventors: Tadahiro Ohmi, Shigetoshi Sugawa, Akinobu Teramoto, Hiroshi Akahori, Keiichi Nii
  • Patent number: 7148551
    Abstract: A semiconductor energy detector includes a semiconductor substrate comprised of a semiconductor of a first conductivity type, into which an energy ray of a predetermined wavelength range is incident from an incident surface thereof. A semiconductor energy detector includes a plurality of diffusion regions of a second conductivity type comprised of a semiconductor of a second conductivity type and a diffusion region of the first conductivity type comprised of a semiconductor of the first conductivity type higher in impurity concentration than the semiconductor substrate. The diffusion regions of a second conductivity type and the diffusion region of the first conductivity type are provided on a surface opposite to the incident surface of said semiconductor substrate. Each first conductivity type semiconductor substrate side of pn junctions, formed at the area of interface between the semiconductor substrate and each of the diffusion regions of the second conductivity type, is commonly connected.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: December 12, 2006
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Yasuhito Yoneta, Hiroshi Akahori, Masaharu Muramatsu
  • Publication number: 20060138538
    Abstract: In a P-channel power MIS field effect transistor formed on a silicon surface having substantially a (110) plane, a gate insulation film is used which provides a gate-to-source breakdown voltage of 10 V or more, and planarizes the silicon surface, or contains Kr, Ar, or Xe.
    Type: Application
    Filed: November 22, 2005
    Publication date: June 29, 2006
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Hiroshi Akahori, Keiichi Nii, Takanori Watanabe
  • Patent number: 6992020
    Abstract: A semiconductor device of this invention includes a silicon nitride film formed on a semiconductor substrate and having a density of 2.2 g/cm3 or less, and a silicon oxide film formed on the silicon nitride film in an ambient atmosphere containing TEOS and O3.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: January 31, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Susumu Hiyama, Akihito Yamamoto, Hiroshi Akahori, Shigehiko Saida
  • Publication number: 20050231292
    Abstract: In a jitter generator (phase modulator), worsening of phase noise is restrained and phase modulation accuracy is improved, and the phase modulation accuracy is improved by preventing a change in the detection sensitivity of the phase detector, if any, from affecting a change in the phase modulation index. Also, phase modulation is made possible without lowering the phase modulation accuracy even when an input phase signal increases. In a jitter generator using a PLL circuit, a quadrature modulator to which a modulation signal from a phase signal generator is provided is inserted to an input stage of a phase detector that constitutes the PLL circuit.
    Type: Application
    Filed: March 17, 2005
    Publication date: October 20, 2005
    Inventors: Hiroshi Akahori, Minoru Maeda
  • Patent number: 6929991
    Abstract: The present invention provides a semiconductor device and a method of manufacturing the same improved in reliability of a gate insulating film by increasing a total charge amount Qbd by suppressing a film stress of a gate electrode formed of a polysilicon film, to a low value. Since the film stress is closely related to a film formation temperature, it is possible to reduce the film stress lower than the conventional case by forming a film at as a high temperature as 640° C. or more. At this time, when the film stress decreases, the total charge amount Qbd regulating dielectric breakdown of the film increases, improving reliability of the gate insulating film. It is therefore possible to set the film stress of the gate electrode at 200 MPA or less in terms of absolute value by forming the gate electrode at 640° C. or more.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: August 16, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuuichi Mikata, Shuji Katsui, Hiroshi Akahori
  • Patent number: 6909993
    Abstract: A method for diagnosing failure of a manufacturing apparatus, includes: measuring time series data of characteristics of a reference apparatus which conducts same processes as the manufacturing apparatus, and recording the time series data of the characteristics in a system information storage unit as a system information database; reading out a recipe listed in a process control information database recorded in a process control information storage unit; driving and controlling the manufacturing apparatus, measuring time series data of the characteristics as test data, and outputting the test data in real time, in accordance with the recipe; performing calculations on the test data, and creating failure diagnosis data; and diagnosing the failure of the manufacturing apparatus using the failure diagnosis data and the system information database.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: June 21, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Nakao, Yukihiro Ushiku, Shuichi Samata, Hiroshi Akahori, Ken Ishii
  • Patent number: 6889239
    Abstract: Data other than inserted “0”s are selected by first selectors from among a plurality of data included in input data to which zero value interpolation is carried out at an interpolation circuit. Besides, coefficients by which the data selected by the first selectors should be multiplied are selected by second selectors. The data selected by the first selectors are multiplied by the coefficients selected by second selectors in multiplication circuits. Then, an adding circuit adds all of the multiplied results and outputs the added result as the desired filter characteristic.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: May 3, 2005
    Assignee: Yokogawa Electric Corporation
    Inventor: Hiroshi Akahori
  • Publication number: 20050012171
    Abstract: A semiconductor device of this invention includes a silicon nitride film formed on a semiconductor substrate and having a density of 2.2 g/cm3 or less, and a silicon oxide film formed on the silicon nitride film in an ambient atmosphere containing TEOS and O3.
    Type: Application
    Filed: July 30, 2004
    Publication date: January 20, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Susumu Hiyama, Akihito Yamamoto, Hiroshi Akahori, Shigehiko Saida
  • Patent number: 6841850
    Abstract: A semiconductor device of this invention includes a silicon nitride film formed on a semiconductor substrate and having a density of 2.2 g/cm3 or less, and a silicon oxide film formed on the silicon nitride film in an ambient atmosphere containing TEOS and O3.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: January 11, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Susumu Hiyama, Akihito Yamamoto, Hiroshi Akahori, Shigehiko Saida
  • Publication number: 20040155271
    Abstract: The present invention provides a semiconductor device and a method of manufacturing the same improved in reliability of a gate insulating film by increasing a total charge amount Qbd by suppressing a film stress of a gate electrode formed of a polysilicon film, to a low value. Since the film stress is closely related to a film formation temperature, it is possible to reduce the film stress lower than the conventional case by forming a film at as a high temperature as 640° C. or more. At this time, when the film stress decreases, the total charge amount Qbd regulating dielectric breakdown of the film increases, improving reliability of the gate insulating film. It is therefore possible to set the film stress of the gate electrode at 200 MPA or less in terms of absolute value by forming the gate electrode at 640° C. or more.
    Type: Application
    Filed: February 11, 2004
    Publication date: August 12, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuuichi Mikata, Shuji Katsui, Hiroshi Akahori
  • Patent number: 6772045
    Abstract: A system for determining dry cleaning timing, includes: a manufacturing apparatus configured to process materials assigned by a sequence of lots; an apparatus controller configured to control the manufacturing apparatus and obtaining operational conditions of the manufacturing apparatus as apparatus information; a lot information input terminal configured to obtain process conditions of one of the lots as lot information; an apparatus information storage unit configured to store the apparatus information from the apparatus controller as an apparatus information database; a lot information storage unit configured to store the lot information from the lot information input terminal as a lot information database; and a cleaning determination unit configured to determine timing to perform a dry cleaning of the manufacturing apparatus based on the apparatus information database and the lot information database.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: August 3, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shuji Katsui, Masayuki Tanaka, Masaki Kamimura, Hiroshi Akahori, Ichiro Mizushima, Takashi Nakao, Akihito Yamamoto, Shigehiko Saida, Yoshitaka Tsunashima, Yuuichi Mikata
  • Publication number: 20040108575
    Abstract: In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.
    Type: Application
    Filed: December 2, 2003
    Publication date: June 10, 2004
    Applicant: Tadahiro OHMI
    Inventors: Tadahiro Ohmi, Shigetoshi Sugawa, Akinobu Teramoto, Hiroshi Akahori, Keiichi Nii
  • Patent number: 6724062
    Abstract: A semiconductor energy detector as disclosed herein is arranged so that an aluminum wiring pattern is formed on the front side of transfer electrodes of a CCD vertical shift register, which pattern includes meander-shaped auxiliary wirings for performing auxiliary application/supplement and additional wirings for performing auxiliary supplement of transfer voltages in a way independent of the auxiliary wirings with respective ones of such wirings being connected to corresponding transfer electrodes to thereby avoid a problem as to lead resistivities at those transfer electrodes made of polycrystalline silicon, thus achieving the intended charge transfer at high speeds with high efficiency.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: April 20, 2004
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Hiroshi Akahori, Hisanori Suzuki, Kazuhisa Miyaguchi, Masaharu Muramatsu, Koei Yamamoto
  • Patent number: 6723994
    Abstract: A semiconductor energy detector having a region for detection and charge accumulation/transfer where a two-dimensional pixel array is formed on a surface of a semiconductor substrate on which energy rays become incident, is characterized in that the region for detection and charge accumulation/transfer comprises a plurality of transfer electrodes formed in each pixel, and an excess charge removing means arranged in correspondence with one of the transfer electrodes in each pixel.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: April 20, 2004
    Assignee: Hamamatsu Photonics K.K.
    Inventor: Hiroshi Akahori