Patents by Inventor Hiroshi Furuta

Hiroshi Furuta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8471336
    Abstract: A semiconductor integrated circuit device includes a gate electrode of at least one of a P-channel MISFET (metal-insulator-semiconductor field-effect transistor) and an N-channel MISFET provided in a direction parallel to a direction of a well isolation boundary phase between the P-channel MISFET and the N-channel MISFET, a first diffusion layer having a same conductivity type as that of a drain diffusion layer of one of a plurality of ones of the MISFET provided in two regions with a drain diffusion layer of the MISFET therebetween through an isolation respectively in a direction orthogonal to the gate electrode, and a second diffusion layer having a conductivity type different from that of the drain diffusion layer of the one of the plurality of ones of the MISFET provided between the well isolation boundary phase and one of a source diffusion layer and the drain diffusion layer.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: June 25, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Furuta, Shouzou Uchida, Muneaki Matsushige, Junji Monden
  • Patent number: 8445943
    Abstract: A semiconductor integrated circuit device includes: a plurality of data holding circuits; and a plurality of wells. The plurality of data holding circuits is provided in a substrate of a first conductive type. Each of the plurality of data holding circuits includes a first well of the first conductive type and a second well of a second conductive type different from the first conductive type. The plurality of wells is arranged in two directions for the each of the plurality of data holding circuits.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: May 21, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroshi Furuta
  • Patent number: 8445951
    Abstract: A semiconductor integrated circuit device, includes a first electrode including a first semiconductor layer formed on a substrate, a side surface insulating film formed on at least a part of a side surface of the first electrode, an upper surface insulating film formed on the first electrode and the side surface insulating film, a second electrode which covers the side surface insulating film and the upper surface insulating film, and a fin-type field effect transistor. The first electrode, the side surface insulating film, and the second electrode constitute a capacitor element. A thickness of the upper surface insulating film between the first electrode and the second electrode is larger than a thickness of the side surface insulating film between the first electrode and the second electrode, and the fin-type field effect transistor includes a second semiconductor layer which protrudes with respect to the plane of the substrate.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: May 21, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Furuta, Takayuki Shirai, Shunsaku Naga
  • Patent number: 8399954
    Abstract: A semiconductor integrated circuit device according to an embodiment of the invention includes: a protective element formed on a semiconductor substrate; and a plurality of wiring layers composed of insulating layers including a layer that is a low dielectric-constant film, and metal lines, in which a metal line in a second wiring layer and a metal line in a first wiring layer among the plurality of wiring layers extend from the other region above the semiconductor substrate to a region electrically connected with the protective element.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: March 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroshi Furuta
  • Publication number: 20130033308
    Abstract: A semiconductor integrated circuit device includes a functional circuit part that includes a plurality of field effect transistors, a mode control circuit that receives a first control signal and that generates a second control signal that is used to change a logic state of the functional circuit part, an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal, and a control circuit that receives the second control signal and that generates a third control signal to the output control circuit. During a time period when the functional circuit part changes a logic state according to the second control. signal, the output control circuit inverts the output signal of the functional circuit part according to the third control signal.
    Type: Application
    Filed: September 15, 2012
    Publication date: February 7, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Kenjyu Shimogawa, Hiroshi Furuta
  • Patent number: 8310297
    Abstract: Disclosed is a semiconductor device including a mode control circuit that, when a standby control signal is in an activated state, based on a timer output signal from a timer circuit, generates a MODE control output signal that changes a logic state of a functional circuit part at every prescribed time interval, and an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal; based on a delay output signal generated by delaying a MODE control output signal by a delay circuit. While the functional circuit part is changing the logic state by the MODE control output signal, the output control circuit does not transfer the functional circuit part output signal to output, but holds and outputs a functional circuit part output signal immediately before the functional circuit part changes the logic state by the MODE control output signal.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kenjyu Shimogawa, Hiroshi Furuta
  • Publication number: 20120241860
    Abstract: A semiconductor integrated circuit device includes a gate electrode of at least one of a P-channel MISFET (metal-insulator-semiconductor field-effect transistor) and an N-channel MISFET provided in a direction parallel to a direction of a well isolation boundary phase between the P-channel MISFET and the N-channel MISFET, a first diffusion layer having a same conductivity type as that of a drain diffusion layer of one of a plurality of ones of the MISFET provided in two regions with a drain diffusion layer of the MISFET therebetween through an isolation respectively in a direction orthogonal to the gate electrode, and a second diffusion layer having a conductivity type different from that of the drain diffusion layer of the one of the plurality of ones of the MISFET provided between the well isolation boundary phase and one of a source diffusion layer and the drain diffusion layer.
    Type: Application
    Filed: April 2, 2012
    Publication date: September 27, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Hiroshi Furuta, Shouzou Uchida, Muneaki Matsushige, Junji Monden
  • Patent number: 8269126
    Abstract: The invention provides a gas insulated switchgear, and a method for detecting arc damage in a part used in a gas insulated switchgear, which detect directly when an electric contact or a peripheral part reaches an initially set wear limit. An insulating nozzle of a circuit breaker contains a marking substance that releases a gaseous substance inside a circuit breaker gas container as a result of wear by an arc. For ensuring heat resistance and insulation properties, the insulating nozzle is ordinarily formed of a fluororesin, but in the present invention, it is formed of the ordinarily used fluororesin having uniformly mixed therein, as the marking substance, a chlorine-containing resin which has excellent heat resistance and insulation properties such as polyvinylidene chloride.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: September 18, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukio Kanazawa, Masahiro Hanai, Hiroshi Furuta
  • Publication number: 20120228737
    Abstract: A semiconductor integrated circuit device includes a power supply line connected to a power supply terminal, a ground line connected to a ground terminal and a plurality of capacitors connected in parallel between the power supply line and the ground line. The plurality of capacitors include a first capacitor arranged at a first distance from one of the terminals and a second capacitor arranged at a second distance which is larger than the first distance from the one of the terminals, and the first capacitor has a larger area than the second capacitor.
    Type: Application
    Filed: May 18, 2012
    Publication date: September 13, 2012
    Inventor: Hiroshi FURUTA
  • Patent number: 8217460
    Abstract: A semiconductor device has an SOI (Silicon On Insulator) structure and comprising a P-channel FET and an N-channel FET which are formed on an insulating film. The semiconductor device includes: at least two of first, second, third and fourth PN-junction elements. The first PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of source/drain regions of the P-channel FET and the N-channel FET, respectively. The second PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of the source/drain region and a channel region in the P-channel FET, respectively. The third PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of a channel region and the source/drain region in the N-channel FET, respectively.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: July 10, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroshi Furuta
  • Publication number: 20120153370
    Abstract: A semiconductor integrated circuit device, includes a first electrode including a first semiconductor layer formed on a substrate, a side surface insulating film formed on at least a part of a side surface of the first electrode, an upper surface insulating film formed on the first electrode and the side surface insulating film, a second electrode which covers the side surface insulating film and the upper surface insulating film, and a fin-type field effect transistor. The first electrode, the side surface insulating film, and the second electrode constitute a capacitor element. A thickness of the upper surface insulating film between the first electrode and the second electrode is larger than a thickness of the side surface insulating film between the first electrode and the second electrode, and the fin-type field effect transistor includes a second semiconductor layer which protrudes with respect to the plane of the substrate.
    Type: Application
    Filed: February 28, 2012
    Publication date: June 21, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi FURUTA, Takayuki Shirai, Shunsaku Naga
  • Patent number: 8169037
    Abstract: A MISFET includes a drain diffusion layer of a first conductivity type, a source diffusion layer of the first conductivity type, a gate electrode, and a substrate/well of a second conductivity type. In the MISFET, first diffusion layers of the first conductivity type are provided at two or more positions at predetermined intervals with an isolation therebetween respectively. The two or more positions are facing at least two sides of the element isolation insulation around the drain diffusion layer. A second diffusion layer of the second conductivity type is provided so as to be close to or to come in contact with the source diffusion layer.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: May 1, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Furuta, Shouzou Uchida, Muneaki Matsushige, Junji Monden
  • Publication number: 20110316052
    Abstract: In addition to a memory macro region and functional circuit regions on a substrate, a semiconductor integrated circuit device includes a dummy pattern region 40 arranged between the functional circuit regions and between the memory macro region 10 and the functional circuit regions and including a dummy pattern. The dummy pattern has a pattern identical to that of diffusion layers and gate electrodes of a memory cell pattern in a memory cell array region. An area ratio of dummy diffusion layer(s) and dummy gate electrode(s) in the dummy pattern region is equal to or greater than that of the diffusion layers and the gate electrode(s) in the memory cell array region.
    Type: Application
    Filed: June 1, 2011
    Publication date: December 29, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi FURUTA, Takaaki KOBAYASHI, Hirofumi AZUHATA, Tomoya MORITA, Ryuichi OKAMURA, Toshifumi TAKAHASHI
  • Patent number: 8054705
    Abstract: A semiconductor integrated circuit has K (K is a natural number of 2 or more) number of memory cells coupled to a same word line, and multiple sense amplifier circuits coupled to the memory cells. The multiple sense amplifier circuits are divided into N (N is a natural number of 2 or more) number of groups. Among the N number of groups, after a first group of sense amplifier circuits is activated and carrying out a predetermined read-out operation, a second group of the sense amplifier circuits is activated and the predetermined read-out operation is carried out, and an Nth group of the sense amplifier circuits is activated sequentially to carry out the predetermined read-out operation.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: November 8, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Kenjyu Shimogawa, Hiroshi Furuta
  • Patent number: 8050108
    Abstract: Provided is a destructive readout semiconductor memory device capable of avoiding concentration of a writeback current, in which a switch circuit (24) is provided between each bit line (21) and each sense amplifier (26). In writeback, the switch circuits are turned on at staggered time points. In readout, the switch circuits are turned on to read memory cell data to the sense amplifiers while the sense amplifiers are turned off, and the switch circuits are then turned off once. After that, the sense amplifiers are turned on to amplify the read data. The switch circuits are subsequently divided into groups and turned on again to write back the data amplified by the sense amplifiers to the memory cells. The switch circuits are divided into groups to be turned on at staggered time points during the writeback, to thereby avoid concentration of the writeback current in one time period.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: November 1, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Kenjiyu Shimogawa, Hiroshi Furuta, Shunsaku Naga, Takayuki Shirai
  • Patent number: 8004306
    Abstract: A semiconductor device according to an embodiment of the present invention includes: an oscillating circuit including a plurality of logic circuits connected in series; and an error detecting circuit receiving output signals of at least two of the plurality of logic circuits, and suspending an operation of the oscillating circuit to notify other blocks of the oscillating circuit that an error occurs in the oscillating circuit if a phase difference between the output signals is not within a predetermined phase difference range.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: August 23, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Takahashi, Hiroshi Furuta
  • Publication number: 20110199140
    Abstract: Disclosed is a semiconductor device including a mode control circuit that, when a standby control signal is in an activated state, based on a timer output signal from a timer circuit, generates a MODE control output signal that changes a logic state of a functional circuit part at every prescribed time interval, and an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal; based on a delay output signal generated by delaying a MODE control output signal by a delay circuit. While the functional circuit part is changing the logic state by the MODE control output signal, the output control circuit does not transfer the functional circuit part output signal to output, but holds and outputs a functional circuit part output signal immediately before the functional circuit part changes the logic state by the MODE control output signal.
    Type: Application
    Filed: February 14, 2011
    Publication date: August 18, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Kenjyu Shimogawa, Hiroshi Furuta
  • Patent number: 7993964
    Abstract: A manufacturing method of a semiconductor device includes forming an oxide semiconductor thin film layer of zinc oxide, wherein at least a portion of the oxide semiconductor thin film layer in an as-deposited state includes lattice planes having a preferred orientation along a direction perpendicular to the substrate and a lattice spacing d002 of at least 2.619 ?.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: August 9, 2011
    Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.
    Inventors: Takashi Hirao, Takahiro Hiramatsu, Mamoru Furuta, Hiroshi Furuta, Tokiyoshi Matsuda
  • Patent number: 7989846
    Abstract: The semiconductor device includes first and second common source semiconductor layers respectively extending in a first direction, first and second logic gate circuits respectively composed of at least one three-dimensional P-type FET and a three-dimensional N-type FET. The sources of the three-dimensional P-type FETs in the first and second logic gate circuits are joined to the first common source semiconductor layer. The sources of the three-dimensional N-type FETs in the first and second logic gate circuits are joined to the second common source semiconductor layer. The semiconductor layers of the three-dimensional P-type and N-type FETs in the first logic gate circuit are joined in their drain side, and The semiconductor layers of the three-dimensional P-type and N-type FETs in the second logic gate circuit are joined in their drain side. The dissipation of the FinFET can be improved.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: August 2, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroshi Furuta
  • Publication number: 20110175197
    Abstract: A semiconductor integrated circuit device includes: a plurality of data holding circuits; and a plurality of wells. The plurality of data holding circuits is provided in a substrate of a first conductive type. Each of the plurality of data holding circuits includes a first well of the first conductive type and a second well of a second conductive type different from the first conductive type. The plurality of wells is arranged in two directions for the each of the plurality of data holding circuits.
    Type: Application
    Filed: January 20, 2011
    Publication date: July 21, 2011
    Inventor: Hiroshi FURUTA