Patents by Inventor Hiroshi Hozoji

Hiroshi Hozoji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030071331
    Abstract: A semiconductor device which includes a semiconductor chip, an insulating film formed on the semiconductor chip, a plurality of projected stress relaxation materials formed on the insulating film, projected electrodes covering at least tops of the stress relaxation materials, and wiring lines for electrically connecting the projected electrodes and element electrodes of the semiconductor chip.
    Type: Application
    Filed: October 17, 2002
    Publication date: April 17, 2003
    Inventors: Yoshihide Yamaguchi, Shigeharu Tsunoda, Hiroyuki Tenmei, Hiroshi Hozoji, Naoya Kanda
  • Patent number: 6531760
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: March 11, 2003
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Publication number: 20030002260
    Abstract: The invention provides an electronic apparatus having a metal core substrate including a metal plate, an insulating layer formed on the metal plate and a conductive layer formed on the insulating layer, and an electronic part, and to which the conductive layer and a terminal of the electronic part are connected. In the electronic apparatus, a member having a high thermal conductivity is arranged so as to be in contact with both of the metal plate and the electronic part. Accordingly, a heat radiating property of the electronic apparatus is increased.
    Type: Application
    Filed: May 17, 2002
    Publication date: January 2, 2003
    Inventors: Takehiko Hasebe, Takehide Yokozuka, Nobuyuki Ushifusa, Masahide Harada, Eiji Matsuzaki, Hiroshi Hozoji
  • Publication number: 20020180027
    Abstract: A multi-chip module including semiconductor devices and a wiring substrate for mounting the semiconductor devices in which the wiring substrate comprises a glass substrate having holes formed by sand blasting and a wiring layer formed on the surface of the glass substrate and having wiring and an insulation layer.
    Type: Application
    Filed: November 29, 2001
    Publication date: December 5, 2002
    Inventors: Yoshihide Yamaguchi, Takao Terabayashi, Hiroyuki Tenmei, Hiroshi Hozoji, Naoya Kanda
  • Publication number: 20020180015
    Abstract: A multi-chip module including semiconductor devices and a wiring substrate for mounting the semiconductor devices in which the wiring substrate comprises a glass substrate having holes formed by sand blasting and a wiring layer formed on the surface of the glass substrate and having wiring and an insulation layer.
    Type: Application
    Filed: November 30, 2001
    Publication date: December 5, 2002
    Inventors: Yoshihide Yamaguchi, Takao Terabayashi, Hiroyuki Tenmei, Hiroshi Hozoji, Naoya Kanda
  • Publication number: 20020079575
    Abstract: A semiconductor module, comprising a wiring substrate on which wiring is formed, a semiconductor device electrically connected to the wiring formed on the wiring substrate, and an external connection terminal arranged on the semiconductor device mounted side of the wiring substrate so as to be a connected portion between the wiring and the outside electrically connected thereto, wherein there is formed an insulating resin layer thicker than the semiconductor device between the wiring substrate and the external connection terminal.
    Type: Application
    Filed: August 16, 2001
    Publication date: June 27, 2002
    Inventors: Hiroshi Hozoji, Yoshihide Yamaguchi, Naoya Kanda, Shigeharu Tunoda, Hiroyuki Tenmei
  • Publication number: 20020063332
    Abstract: The object of the present invention is to realize a semiconductor device enabling a flip chip connection without use of underfill.
    Type: Application
    Filed: March 20, 2001
    Publication date: May 30, 2002
    Inventors: Yoshihide Yamaguchi, Hiroyuki Tenmei, Kosuke Inoue, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Naoya Kanda, Madoka Minagawa, Ichiro Anjo, Asao Nishimura, Kenji Ujiie, Akira Yajima
  • Patent number: 6326681
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: December 4, 2001
    Assignee: Hitachi, LTD
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Patent number: 6303982
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: January 30, 2001
    Date of Patent: October 16, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Publication number: 20010008302
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Application
    Filed: January 30, 2001
    Publication date: July 19, 2001
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto
  • Patent number: 6204552
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: January 12, 2000
    Date of Patent: March 20, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Patent number: 6130114
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: April 13, 1999
    Date of Patent: October 10, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjoh, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto
  • Patent number: 6124629
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: October 8, 1998
    Date of Patent: September 26, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Patent number: 6100580
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: October 7, 1998
    Date of Patent: August 8, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Patent number: 6100115
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: August 8, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Patent number: 6081023
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: April 9, 1999
    Date of Patent: June 27, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjoh, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto
  • Patent number: 6072231
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: April 28, 1998
    Date of Patent: June 6, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjoh, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto
  • Patent number: 6069029
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: April 15, 1998
    Date of Patent: May 30, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Patent number: 6018191
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: March 5, 1998
    Date of Patent: January 25, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjoh, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto
  • Patent number: 5981315
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: October 6, 1998
    Date of Patent: November 9, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjoh, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto