Patents by Inventor Hiroshi Kaneta

Hiroshi Kaneta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030148178
    Abstract: The battery is constituted to satisfy B/A≧0.57, wherein “A” represents a width of an active material region and “B” represents a width of each electrode terminal.
    Type: Application
    Filed: January 28, 2003
    Publication date: August 7, 2003
    Applicant: NEC CORPORATION
    Inventor: Hiroshi Kaneta
  • Publication number: 20030124416
    Abstract: A battery module includes a battery cell having a laminate overcoat, a pair of rubber sheets, a pair of pressure plates, and a pair of housing members from the internal to the external of the battery module. An intervention member including four poles is interposed between the pressure plate and the housing member at the central area of the battery cell to alleviate the stress concentration on the peripheral area of the battery cell. The intervention member may be formed separately from or integrated with the pressure plate.
    Type: Application
    Filed: December 26, 2002
    Publication date: July 3, 2003
    Applicant: NEC CORPORATION
    Inventor: Hiroshi Kaneta
  • Patent number: 6528382
    Abstract: A semiconductor device comprises a silicon substrate 10 of a resistivity above or equal to 800 &OHgr;·cm and an oxygen concentration under or equal to 5×1017 cm−3, and an inductor 32b formed in the silicon substrate. A concentration of oxygen contained in the silicon substrate is set to be low, whereby the silicon substrate is less vulnerable to thermal donor effect, and even in a case that a silicon substrate of high resistivity is used, a semiconductor device which suppresses conversion of a conduction type of the silicon substrate while having an inductance of high Q. It is not necessary to bury a highly resistive layer in the silicon substrate, whereby a semiconductor device having an inductance of high Q can be fabricated by simple fabrication steps, which contributes to cost reduction of the semiconductor device.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: March 4, 2003
    Assignee: Fujitsu Limited
    Inventors: Tsunenori Yamauchi, Hiroshi Kaneta, Katsuhiro Homma
  • Publication number: 20020064923
    Abstract: A semiconductor device comprises a silicon substrate 10 of a resistivity above or equal to 800 &OHgr;·cm and an oxygen concentration under or equal to 5×1017 cm−3, and an inductor 32b formed in the silicon substrate. A concentration of oxygen contained in the silicon substrate is set to be low, whereby the silicon substrate is less vulnerable to thermal donor effect, and even in a case that a silicon substrate of high resistivity is used, a semiconductor device which suppresses conversion of a conduction type of the silicon substrate while having an inductance of high Q. It is not necessary to bury a highly resistive layer in the silicon substrate, whereby a semiconductor device having an inductance of high Q can be fabricated by simple fabrication steps, which contributes to cost reduction of the semiconductor device.
    Type: Application
    Filed: June 19, 2001
    Publication date: May 30, 2002
    Applicant: Fujitsu Limited
    Inventors: Tsunenori Yamauchi, Hiroshi Kaneta, Katsuhiro Homma
  • Patent number: 5286658
    Abstract: A semiconductor device is produced by a process for intrinsic gettering heat treatment of a silicon crystal in which the concentration of C--O complex defects destined to form seeds for oxygen precipitation in the silicon crystal is increased or an amount of oxygen precipitate in the silicon crystal is controlled, to thereby eliminate the dispersion of the amount from one crystal to another. In the heat treatment of the silicon crystal, the amount of oxygen precipitation can be controlled with a high accuracy.
    Type: Grant
    Filed: March 5, 1992
    Date of Patent: February 15, 1994
    Assignee: Fujitsu Limited
    Inventors: Yoshimi Shirakawa, Hiroshi Kaneta
  • Patent number: 5066599
    Abstract: A silicon crystal evaluation method includes the step of measuring, at room temperature, an intensity of an oxygen impurity infrared absorption peak of each of a plurality of silicon crystals at a wavenumber of 1107.+-.3cm.sup.-1, Each of the silicon crystals contains oxygen impurities, the silicon crystals including an evaluated silicon crystal having an unknown thermal history and reference silicon crystals having respective known thermal histories. The second step is to measure, at a temperature equal to or lower than 10K, an intensity of an oxygen impurity infrared absorption peak of each of the silicon crystals at a predetermined wavenumber. A third step is to calculate a first peak intensity ratio between the intensity of the oxygen impurity infrared absorption peak of each of the silicon crystals at 1107.+-.cm.sup.-1 and the intensity of the oxygen impurity infrared absorption peak at the predetermined wavenumber.
    Type: Grant
    Filed: July 23, 1990
    Date of Patent: November 19, 1991
    Assignees: Fujitsu Limited, Jeol, Ltd.
    Inventors: Hiroshi Kaneta, Shuichi Muraishi
  • Patent number: 4803884
    Abstract: A method for measuring lattice defects in semiconductor such as a silicon crystal, detects an ultrasonic velocity of an ultrasonic pulse propagating through the semiconductor to which heat is variably applied. An elastic constant of the semiconductor is calculated from the ultrasonic velocity, and a concentration or density of lattice defects of the semiconductor is obtained by converting the elastic constant.
    Type: Grant
    Filed: December 22, 1987
    Date of Patent: February 14, 1989
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Kaneta, Tsutomu Ogawa, Haruhisa Mori, Kunihiko Wada
  • Patent number: 4480682
    Abstract: An apparatus for freezing fertilized ova, spermatozoa or the like has a heat transfer bottom board block formed at the lower end of a heat insulating peripheral wall with a lower refrigerant passage capable of flowing refrigerant. A bottom board temperature sensor is attached to the bottom board block, an upper heat transfer block is placed on the bottom board block through a heat insulating joint member, formed with an upper refrigerant passage for flowing the refrigerant. A temperature control heater, an upper block temperature sensor, a plurality of erecting tube charging spaces of tubes opened at the top thereof with the bottom board block as a bottom member are disposed between the peripheral wall and the upper block in such a manner that the tubes erected and charged into the spaces are cooled at the lower ends thereof by said bottom board block and at the upper part containing articles to be frozen such as fertilized ova, spermatozoa or the like are contained in buffer solution in said tubes.
    Type: Grant
    Filed: January 9, 1984
    Date of Patent: November 6, 1984
    Assignee: Hoxan Corporation
    Inventors: Hiroshi Kaneta, Nobuo Sakao, Yasuo Kuraoka