Patents by Inventor Hiroshi Shiba

Hiroshi Shiba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4450470
    Abstract: An integrated circuit device of large scale integration and a method of manufacturing the same makes possible high density packing of circuit elements by eliminating a great number of very minute contact holes. Instead, a circuit-element connector comprised of a polycrystalline silicon wiring path is formed by selective oxidation. Impurity atoms are introduced into the semiconductor substrate through the polycrystalline silicon circuit-element connector to form a desired circuit element. A layer of high-conductive material is provided on the polycrystalline silicon layer.
    Type: Grant
    Filed: February 12, 1979
    Date of Patent: May 22, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Hiroshi Shiba
  • Patent number: 4306915
    Abstract: A semiconductor device suitable for a high-density integrated circuit is disclosed. The semiconductor device comprises an electrode wiring layer made of silicon with a substantially flat surface deposited on a major surface of a semiconductor substrate, the periphery of which is filled with an insulating layer produced by selectively oxidizing the silicon, a first impurity doped region formed in the semiconductor substrate in self-aligning relation with the electrode wiring layer, and a second impurity doped region coupled to the first impurity doped region and underlain the insulating layer.
    Type: Grant
    Filed: April 23, 1979
    Date of Patent: December 22, 1981
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Hiroshi Shiba
  • Patent number: 4243455
    Abstract: An improved simple and cheap method of forming electrode connector for liquid crystal display device has been found. This novel method eliminates difficulties in complicated compression molding process required a high accuracy of dimensions in a molded electrode connector.
    Type: Grant
    Filed: July 20, 1978
    Date of Patent: January 6, 1981
    Assignee: Nippon Graphite Industries, Ltd.
    Inventors: Hiroshi Shiba, Katsuhiro Murata
  • Patent number: 4188636
    Abstract: A semiconductor device is disclosed in which a protrusion is interposed between a bump terminal electrode and the peripheral edge of the semiconductor substrate.
    Type: Grant
    Filed: March 29, 1978
    Date of Patent: February 12, 1980
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Susumu Sato, Hiroshi Shiba
  • Patent number: 4127931
    Abstract: In a method for fabricating a semiconductor device, a polycrystalline film deposited on a main surface of a substrate is subjected to selective oxidation to form polycrystalline silicon electrode wiring paths separated by silicon oxide. An impurity of a conductivity type opposite to that of the substrate is introduced through at least one of the wiring paths into the substrate. Also disclosed is a novel semiconductor device fabricated according to this process which has a reduced junction area and a shortened junction-to-electrode distance.
    Type: Grant
    Filed: November 2, 1977
    Date of Patent: December 5, 1978
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Hiroshi Shiba
  • Patent number: 4104785
    Abstract: In fabricating a large-scale semiconductor integrated circuit, a wiring layer within each unit cell is formed of a conductive material which is hard and highly resistant to corrosion, and test pads for each unit cell are formed of a conductive material which is soft and low resistant to corrosion. After testing each unit cell by using the test pads, the test pads are etched away. If necessary, pad relocation wiring which is used to substitute a good unit cell for a bad unit cell may be formed of the hard and highly corrosion-resistant conductive material, and an intercell wiring layer may be formed of the soft and low corrosion-resistant conductive material.
    Type: Grant
    Filed: February 23, 1976
    Date of Patent: August 8, 1978
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Hiroshi Shiba, Kenji Kani
  • Patent number: 4074304
    Abstract: In a method for fabricating a semiconductor device, a polycrystalline film deposited on a main surface of a substrate is subjected to selective oxidation to form polycrystalline silicon electrode wiring paths separated by silicon oxide. An impurity of a conductivity type opposite to that of the substrate is introduced through at least one of the wiring paths into the substrate. Also disclosed is a novel semiconductor device fabricated according to this process which has a reduced junction area and a shortened junction-to-electrode distance.
    Type: Grant
    Filed: March 2, 1977
    Date of Patent: February 14, 1978
    Assignee: Nippon Electric Company, Ltd.
    Inventor: Hiroshi Shiba
  • Patent number: 4063901
    Abstract: A method of manufacturing a semiconductor device is disclosed, in which a polycrystalline silicon layer is formed over a semiconductor substrate coated with an insulating layer with a window and a first kind of impurity is doped to a first predetermined portion of the polycrystalline silicon layer to a depth at least reaching the surface of the semiconductor substrate. Then a peripheral of the doped portion of the polycrystalline silicon layer is converted into an insulator, and a second kind of impurity is doped into a second predetermined portion of the polycrystalline silicon layer to a depth at least reaching the surface of the semiconductor substrate, thereby providing electrode wiring paths including the first and second predetermined portions.
    Type: Grant
    Filed: March 29, 1977
    Date of Patent: December 20, 1977
    Assignee: Nippon Electric Company, Ltd.
    Inventor: Hiroshi Shiba
  • Patent number: 3939047
    Abstract: A thermally stable semiconductor device is disclosed in which a thin aluminum film is formed over a silicon oxide film selectively formed on the silicon substrate. A layer of a metal such as tantalum, tungsten, or molybdenum that does not enter into an alloy reaction with silicon at heat treatment temperatures is formed over the thin aluminum film and is covered with a thick aluminum film. Oxides of the upper thick aluminum layer as well as oxides of the non-alloying metal and the lower aluminum layer are selectively formed in alignment with one another at locations where the electrodes are not formed.
    Type: Grant
    Filed: August 29, 1974
    Date of Patent: February 17, 1976
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Hideo Tsunemitsu, Hiroshi Shiba