Patents by Inventor Hiroshi Sukegawa

Hiroshi Sukegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10490282
    Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: November 26, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroshi Sukegawa, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
  • Patent number: 10482970
    Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: November 19, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Hiroshi Sukegawa
  • Patent number: 10453886
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: October 22, 2019
    Assignee: Sony Corporation
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue
  • Patent number: 10196241
    Abstract: According to one embodiment, an elevator system includes a camera, a passenger detection module and a controller. The camera is capable of imaging a particular range in a direction from a vicinity of a door of a car to a hall when the car arrives at the hall. The passenger detection module detects presence or absence of a passenger who intends to get into the car by focusing on movement of a movable body within a specific area by using a plurality of time-series continuous images which are captured by the camera. The controller controls an opening/closing operation of the door based on a detection result of the passenger detection module. A width of the area is being set greater than at least a width of the door.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: February 5, 2019
    Assignee: TOSHIBA ELEVATOR KABUSHIKI KAISHA
    Inventors: Shuhei Noda, Kentaro Yokoi, Hiroshi Sukegawa, Yukari Murata, Sayumi Kimura
  • Publication number: 20180342067
    Abstract: A moving object tracking system includes an input unit, a detection unit, a creating unit, a weight calculating unit, a calculating unit, and an output unit. The detection unit detects all tracking target moving objects from each of input images input. The creating unit creates a combination of a path that links each moving object detected in a first image to each moving object detected in a second image, a path that links each moving object detected in the first image to an unsuccessful detection in the second image, and a path that links an unsuccessful detection in the first image to each moving object detected in the second image. The calculating unit calculates a value for the combination of the paths to which weights are allocated. The output unit outputs a tracking result.
    Type: Application
    Filed: August 3, 2018
    Publication date: November 29, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroo SAITO, Toshio Sato, Osamu Yamaguchi, Hiroshi Sukegawa
  • Publication number: 20180330792
    Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.
    Type: Application
    Filed: July 26, 2018
    Publication date: November 15, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Hiroshi SUKEGAWA, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
  • Patent number: 10062438
    Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: August 28, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroshi Sukegawa, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
  • Publication number: 20180151229
    Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
    Type: Application
    Filed: January 26, 2018
    Publication date: May 31, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru SHIBATA, Hiroshi Sukegawa
  • Patent number: 9966146
    Abstract: According to one embodiment, a controller groups a plurality of memory cells in each of the pages into a plurality of groups. The plurality of groups includes a first group and a second group. In a case of reading data from a first page, The controller performs first reading. The first reading includes reading data from the first page by using a first operation parameter for the first group. The controller performs second reading. The second reading includes reading data from the first page by using a second operation parameter for the second group. The controller merges first read data and second read data, and return the merged data as read data read from the first page. The first read data is acquired by the first reading. The second read data is acquired by the second reading.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: May 8, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daiki Watanabe, Hiroshi Sukegawa, Hiroshi Yao, Tokumasa Hara, Naomi Takeda
  • Patent number: 9928913
    Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: March 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Hiroshi Sukegawa
  • Publication number: 20180082439
    Abstract: An image collation system comprising: a detection unit that detects an object from an image acquired by imaging a predetermined position using an imaging unit; a tracking unit that tracks an object image of the same object; a selection unit that calculates an evaluated value for each of the object images of the same object and selects the object image of which the evaluated value is equal to or greater than a predetermined value as a best shot image; a collation unit that performs a collation process of collating the best shot image with a registered image and determining whether the object present at the predetermined position is a previously registered object; and a display that displays a performance result of the collation process, the image collation system including a storage unit that stores the best shot image; and a preparation unit that updates or re-prepares an evaluation expression that calculates the evaluated value.
    Type: Application
    Filed: September 6, 2017
    Publication date: March 22, 2018
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Infrastructure Systems & Solutions Corporation
    Inventors: Kota SAITO, Yusuke TAZOE, Hiroo SAITO, Hiroshi SUKEGAWA
  • Patent number: 9905284
    Abstract: A storage device includes a memory cell array, a voltage detector disposed to detect a voltage of power supplied to the memory cell array, and a controller. The controller is configured to carry out reading of data from a target memory cell and then rewriting of the data in the target memory cell, if the detected voltage is above a threshold when a prompt of a read operation with respect to the target memory cell occurs, and prohibit the reading operation from being started, if the detected voltage is below the threshold when the prompt occurs.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: February 27, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Sukegawa, Yoshihiro Ueda, Kenichiro Yoshii
  • Patent number: 9880767
    Abstract: A memory system includes a memory which asserts a high-power-consumption operation output when an amount of the power consumption is high in internal operations in respective operations, and a controller which has an interface function between a host and the memory and receives the high-power-consumption operation output. The controller switches an operation mode thereof to a low power consumption mode when the high-power-consumption operation output is asserted.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: January 30, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroshi Sukegawa
  • Patent number: 9817982
    Abstract: According to one embodiment, an identity authentication system includes a detecting unit that detects an identity theft by determining whether a photographing target is a living body or a non-living body, a collating unit that performs identity collation based on a photographed image, and a control unit that controls execution timing of a detection process performed by the detecting unit and an identity collating processing performed by the collating unit and, in a case where the detection performed by the detecting unit is performed for a first number of times, performs the collation process performed by the collating unit, wherein the first number of times is set in consideration of a tradeoff between a required intensity of security and convenience of a user using the identity authentication system.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: November 14, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroo Saito, Hiroshi Sukegawa
  • Patent number: 9807090
    Abstract: According to one embodiment, a person authentication method includes obtaining, from a medium carried by a person who passes through a first position, first information indicating the gender and the age of the person; performing a first authentication operation with respect to a person whose face image is included in a first image obtained by capturing a person passing through the first position; and setting, as the first authentication operation, an authentication operation to be performed using the face image of a person having the gender and the age specified in the first information.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: October 31, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroo Saito, Hiroshi Sukegawa
  • Patent number: 9799406
    Abstract: A memory system includes a memory device, and a controller which controls the memory device. The memory device includes a plurality of memory cells capable of rewriting data, a plurality of word lines connected to the plurality of memory cells, a page including the plurality of memory cells connected to the same word line, a plane including a plurality of pages, a memory cell array including a plurality of planes, and a plurality of word line drivers which apply voltages to the plurality of word lines, and a plurality of switches provided for each plane and which assigns the word line drivers to the word lines.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: October 24, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Manabu Sato, Daiki Watanabe, Hiroshi Sukegawa, Tokumasa Hara, Hiroshi Yao, Naomi Takeda, Noboru Shibata, Takahiro Shimizu
  • Publication number: 20170263301
    Abstract: A storage device includes a memory cell array, a voltage detector disposed to detect a voltage of power supplied to the memory cell array, and a controller. The controller is configured to carry out reading of data from a target memory cell and then rewriting of the data in the target memory cell, if the detected voltage is above a threshold when a prompt of a read operation with respect to the target memory cell occurs, and prohibit the reading operation from being started, if the detected voltage is below the threshold when the prompt occurs.
    Type: Application
    Filed: December 19, 2016
    Publication date: September 14, 2017
    Inventors: Hiroshi SUKEGAWA, Yoshihiro UEDA, Kenichiro YOSHII
  • Publication number: 20170255818
    Abstract: A person verification system includes an imager, a reader, storage, a selector, and a determiner. The imager images a target person trying to pass through a first gate. The reader reads personal information including an image of a person indicated by identification and attributes of the person, from the identification held by the target person. The storage stores plural algorithms, each algorithm is provided for each of the attributes of the person. The selector selects the algorithm for each of the attributes that are included in the personal information, from the storage unit. The determiner calculates the degree of similarity between the captured image and the image included in the personal information, in accordance with the algorithm selected, and determines whether or not the target person is the person indicated by the identification using the degree of similarity calculated.
    Type: Application
    Filed: March 6, 2017
    Publication date: September 7, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kota SAITO, Hiroo SAITO, Hiroshi SUKEGAWA
  • Patent number: 9720772
    Abstract: A memory system according to an embodiment includes a plurality of magnetic nanowires, a read unit that reads data from the magnetic nanowires, a shift control unit that shifts domain walls in the magnetic nanowires, and a read control unit. The read control unit is configured to control the read unit to read the data from the magnetic nanowires in parallel, store two or more of the data read in parallel, and when the data corresponding to a first magnetic nanowire of the magnetic nanowires are delayed or advanced as compared to the data corresponding to a second magnetic nanowire of the magnetic nanowires, determines a misalignment in the data and correct the data based on the misalignment.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: August 1, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Sukegawa, Hiroshi Yao, Kohsuke Harada
  • Publication number: 20170199705
    Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.
    Type: Application
    Filed: August 8, 2016
    Publication date: July 13, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi SUKEGAWA, Ikuo Magaki, Tokumasa Hara, Shirou Fujita