Patents by Inventor Hirotake Fujita

Hirotake Fujita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8956961
    Abstract: A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: February 17, 2015
    Assignee: Rexchip Electronics Corporation
    Inventors: Kazuaki Takesako, Wen-Kuei Hsu, Yoshinori Tanaka, Yukihiro Nagai, Chih-Wei Hsiung, Hirotake Fujita, Tomohiro Kadoya, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Chung-Yung Ai, Yu-Shan Hsu, Wei-Che Chang, Chun-Hua Huang
  • Publication number: 20130234230
    Abstract: A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 12, 2013
    Inventors: Kazuaki Takesako, Wen-Kuei Hsu, Yoshinori Tanaka, Yukihiro Nagai, Chih-Wei Hsiung, Hirotake Fujita, Tomohiro Kadoya, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Chung-Yung Ai, Yu-Shan Hsu, Wei-Che Chang, Chun-Hua Huang
  • Publication number: 20130193511
    Abstract: A vertical transistor structure comprises a substrate, a plurality of pillars formed on the substrate and spaced from each other, a plurality of trenches each formed between two adjacent pillars, a protection layer formed on the surface of a first side wall and the surface of a second side wall of the trench, a first gate and a second gate respectively formed on the protection layer of the first side wall and the second side wall, and a separation layer covering a bottom wall of the trench. The present invention uses the separation layer functioning as an etch stopping layer to the first gate and the second gate while being etched. Further, thickness of the separation layer is used to control the distance between the bottom wall and the first and second gates and define widths of the drain and the source formed in the pillar via ion implantation.
    Type: Application
    Filed: January 26, 2012
    Publication date: August 1, 2013
    Inventors: Hsuan-Yu FANG, Wei-Chih Liu, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Chung-Yung Ai, Yu-Shan Hsu, Wei-Che Chang, Chun-Hua Huang, Kazuaki Takesako, Tomohiro Kadoya, Wen Kuei Hsu, Hirotake Fujita, Yukihiro Nagai, Chih-Wei Hsiung, Yoshinori Tanaka
  • Publication number: 20130157454
    Abstract: A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 20, 2013
    Inventors: Wei-Che CHANG, Chun-Hua Huang, Chung-Yung Ai, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Yu-Shan Hsu, Kazuaki Takesako, Hirotake Fujita, Tomohiro Kadoya, Wen Kuei Hsu, Chih-Wei Hsiung, Yukihiro Nagai, Yoshinori Tanaka
  • Patent number: 8461056
    Abstract: A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: June 11, 2013
    Assignee: Rexchip Electronics Corporation
    Inventors: Wei-Che Chang, Chun-Hua Huang, Chung-Yung Ai, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Yu-Shan Hsu, Kazuaki Takesako, Hirotake Fujita, Tomohiro Kadoya, Wen Kuei Hsu, Chih-Wei Hsiung, Yukihiro Nagai, Yoshinori Tanaka
  • Publication number: 20100093142
    Abstract: A method of fabricating a device is described. A substrate having at least two isolation structures is provided. A first oxide layer and a first conductive layer are sequentially formed on the substrate between the isolation structures. A first nitridation process is performed to form a first nitride layer on the surface of the first conductive layer and a first oxynitride layer on the surface of the isolation structures. A second oxide layer is formed on the first nitride layer and first oxynitride layer. A densification process is performed to oxidize the first oxynitride layer on the surface of the isolation structures. A second nitride layer and a third oxide layer are sequentially formed on the second oxide layer. A second nitridation process is performed to form a third nitride layer on the surface of the third oxide layer. A second conductive layer is formed on the third nitride layer.
    Type: Application
    Filed: October 9, 2008
    Publication date: April 15, 2010
    Applicant: POWERCHIP SEMICONDUCTOR CORP.
    Inventors: Ching-Yuan Ho, Hirotake Fujita, Po-Jui Chiang
  • Publication number: 20080057190
    Abstract: Ink jet recording sheet having excellent glossiness, ink absorptivity, image quality, and long-term preservability in which cracks generated on an ink receiving layer are significantly reduced. The ink jet recording sheet includes a supporting medium; and an ink receiving layer including an inorganic fine particle, a cationic polymer, and a binder, wherein an average primary particle size of the inorganic fine particle is 30 nm or less, and the cationic polymer including: at least one structural unit (a1) expressed by a following general formula (1) or (2): wherein m and n independently represents an integer of 0 to 4, and X represents an acid residue; and at least one structural unit (a2) expressed by a following general formula (3), (4), (5) or (6): wherein R1 to R8 independently represents a hydrogen atom or a C1-C4 alkyl group, and Y and Z independently represents an acid residue.
    Type: Application
    Filed: October 26, 2007
    Publication date: March 6, 2008
    Applicant: OJI Paper Co., LTD.
    Inventors: Mitsuru Kobayashi, Ikuko Furukawa, Hirotake Fujita, Tetsuo Tsuchida
  • Patent number: 7229917
    Abstract: A film-formation method for a semiconductor process includes seed film formation and main film formation. In the seed film formation, a metal-containing raw material gas and a first assist gas to react therewith are supplied into a process container, which accommodates a target substrate having an underlying layer, thereby forming a seed film on the underlying layer by CVD. In the main film formation, the raw material gas and a second assist gas to react therewith are supplied into the process container, thereby forming a main film on the seed film by CVD. The seed film formation includes first and second periods performed alternately and continuously. In each first period, the raw material gas is supplied into the process container while the first assist gas is stopped. In each second period, the first assist gas is supplied into the process container while the raw material gas is stopped.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: June 12, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Takahito Umehara, Masahiko Tomita, Hirotake Fujita, Kazuhide Hasebe
  • Patent number: 7041546
    Abstract: In a capacitor of an MIM (Metal-Insulator-Metal) structure, a silicon-containing high dielectric film (e.g., a hafnium silicate film) containing a silicon atom, as well as a silicon-free high dielectric film (e.g., a tantalum oxide film) containing no silicon atom is interposed between a lower electrode film and an upper electrode film which are made of metal or metal compound. By adding the silicon-containing high dielectric film, a leak current can be suppressed and the change in capacitor capacity accompanied with the change in applied voltage can be reduced.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: May 9, 2006
    Assignee: Tokyo Electron Limited
    Inventors: Yuichiro Morozumi, Kazuhide Hasebe, Shigeru Nakajima, Haruhiko Furuya, Dong-Kyun Choi, Takahito Umehara, Katsushige Harada, Tomonori Fujiwara, Hirotake Fujita
  • Publication number: 20050176261
    Abstract: A film-formation method for a semiconductor process includes seed film formation and main film formation. In the seed film formation, a metal-containing raw material gas and a first assist gas to react therewith are supplied into a process container, which accommodates a target substrate having an underlying layer, thereby forming a seed film on the underlying layer by CVD. In the main film formation, the raw material gas and a second assist gas to react therewith are supplied into the process container, thereby forming a main film on the seed film by CVD. The seed film formation includes first and second periods performed alternately and continuously. In each first period, the raw material gas is supplied into the process container while the first assist gas is stopped. In each second period, the first assist gas is supplied into the process container while the raw material gas is stopped.
    Type: Application
    Filed: October 5, 2004
    Publication date: August 11, 2005
    Inventors: Takahito Umehara, Masahiko Tomita, Hirotake Fujita, Kazuhide Hasebe
  • Publication number: 20050142305
    Abstract: Ink jet recording sheet having excellent glossiness, ink absorptivity, image quality, and long-term preservability in which cracks generated on an ink receiving layer are significantly reduced. The ink jet recording sheet includes a supporting medium; and an ink receiving layer including an inorganic fine particle, a cationic polymer, and a binder, wherein an average primary particle size of the inorganic fine particle is 30 nm or less, and the cationic polymer including: at least one structural unit (a1) expressed by a following general formula (1) or (2): wherein m and n independently represents an integer of 0 to 4, and X represents an acid residue; and at least one structural unit (a2) expressed by a following general formula (3), (4), (5) or (6): wherein R1 to R8 independently represents a hydrogen atom or a C1-C4 alkyl group, and Y and Z independently represents an acid residue.
    Type: Application
    Filed: November 2, 2004
    Publication date: June 30, 2005
    Inventors: Mitsuru Kobayashi, Ikuko Furukawa, Hirotake Fujita, Tetsuo Tsuchida
  • Patent number: 6858565
    Abstract: Disclosed is a thermosensitive recording material comprising a sheet-shaped support and a thermosensitive recording layer which is formed on at least one surface of the support and comprises a colorless or light-colored dye precursor and a color developer capable of reacting with the dye precursor and inducing color formation therein upon application of heat thereto, the color developer comprising a compound represented by the following formula (I) or analog thereof: The thermosensitive recording material has high sensitivity and can prevent white background portions from coloring and recorded images from decolorizing in an environmental resistance test.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: February 22, 2005
    Assignee: Oji Paper Co., Ltd.
    Inventors: Hirotake Fujita, Jun-Ya Kojima, Ayako Shirai, Yoshiyuki Takahashi
  • Publication number: 20040195653
    Abstract: In a capacitor of an MIM (Metal-Insulator-Metal) structure, a silicon-containing high dielectric film (e.g., a hafnium silicate film) containing a silicon atom, as well as a silicon-free high dielectric film (e.g., a tantalum oxide film) containing no silicon atom is interposed between a lower electrode film and an upper electrode film which are made of metal or metal compound. By adding the silicon-containing high dielectric film, a leak current can be suppressed and the change in capacitor capacity accompanied with the change in applied voltage can be reduced.
    Type: Application
    Filed: August 13, 2003
    Publication date: October 7, 2004
    Inventors: Yuichiro Morozumi, Kazuhide Hasebe, Shigeru Nakajima, Haruhiko Furuya, Choi Dong-Kyun, Takahito Umehara, Katsushige Harada, Tomonori Fujiwara, Hirotake Fujita
  • Publication number: 20030040434
    Abstract: Disclosed is a thermosensitive recording material comprising a sheet-shaped support and a thermosensitive recording layer which is formed on at least one surface of the support and comprises a colorless or light-colored dye precursor and a color developer capable of reacting with the dye precursor and inducing color formation therein upon application of heat thereto, the color developer comprising a compound represented by the following formula (I) or analog thereof: 1
    Type: Application
    Filed: May 13, 2002
    Publication date: February 27, 2003
    Inventors: Hirotake Fujita, Jun-Ya Kojima, Ayako Shirai, Yoshiyuki Takahashi