Patents by Inventor Hiroyoshi Haruki

Hiroyoshi Haruki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8499306
    Abstract: A microprocessor executes programs in a pipeline architecture that includes a task register management unit that switches a value of a task register to second register information that is used when a second task is executed after the execution of a first task is completed, if a switch instruction to the second task is issued when a plurality of units executes the first task, and a task manager that switches a value of a task identification information register to a second task identifier after the value is switched to the second register information, and grants each of the plurality of units permission to execute the second task.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: July 30, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyoshi Haruki, Mikio Hashimoto, Takeshi Kawabata
  • Publication number: 20130191670
    Abstract: According to an embodiment, a control device includes a calculator and a setting unit. The calculator is configured to calculate a system processing time indicating a time required for processing executed after a system, the system including a plurality of elements, power to each element being individually controlled, resumes from a sleep state in which the number of elements supplied with power is limited to a predetermined number and an operation of the system is stopped. The setting unit is configured to set a mode indicating an operation state of the system according to the system processing time calculated by the calculator when a resume factor indicating a factor for resuming the system from the sleep state occurs.
    Type: Application
    Filed: December 21, 2012
    Publication date: July 25, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyoshi Haruki, Koichi Fujisaki, Junichi Segawa, Satoshi Shirai, Yusuke Shirota, Akihiro Shibata, Masaya Tarui, Tetsuro Kimura, Tatsunori Kanai, Haruhiko Toyama
  • Publication number: 20130091372
    Abstract: According to an embodiment, a control device includes a receiving unit, a judging unit, an estimating unit, a deciding unit, a directing unit, and a sending unit. The receiving unit is configured to receive an interrupt request requesting a processing device that includes elements capable of being individually subjected to voltage control to execute an interrupt process. The judging unit is configured to judge a state of the elements. The estimating unit is configured to estimate a start-up time for the element to change into an operating mode after power is supplied. The deciding unit is configured to decide a starting point in time at which power supply is to be started on basis of a difference in the start-up times between the elements. The directing unit is configured to direct a power supply unit for supplying power to the elements. The sending unit is configured to send the interrupt request.
    Type: Application
    Filed: September 19, 2012
    Publication date: April 11, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsuro Kimura, Tatsunori Kanai, Haruhiko Toyama, Koichi Fujisaki, Hiroyoshi Haruki, Masaya Tarui, Satoshi Shirai, Akihiro Shibata
  • Publication number: 20130080813
    Abstract: According to an embodiment, a control system includes a detector, an estimating unit, a determining unit, and a controller. The detector detects an idle state. The estimating unit estimates an idle period. When the idle state is detected, the determining unit determines whether a first power consumption when writeback of data which needs to be written back to a main storage device is performed and supply of power to a cache memory is stopped, is larger than a second power consumption when writeback of the data is not performed and supply of power is continued for the idle period. The controller stops the supply of power to the cache memory when the first power consumption is determined to be smaller than the second power consumption and continues the supply of power when the first power consumption is determined to be larger than the second power consumption.
    Type: Application
    Filed: July 24, 2012
    Publication date: March 28, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaya Tarui, Koichi Fujisaki, Hiroyoshi Haruki, Tatsunori Kanai, Haruhiko Toyama, Tetsuro Kimura, Junichi Segawa, Yusuke Shirota, Satoshi Shirai, Akihiro Shibata
  • Publication number: 20130080812
    Abstract: According to an embodiment, a control system includes a processing device; a main storage device to store the data; a cache memory to store part of the data stored; a prefetch unit to predict data highly likely to be accessed and execute prefetch, reading out data in advance onto the cache memory; and a power supply unit. The system further includes: a detecting unit to detect whether the processing device is in an idle state; a determining unit that determines whether to stop the supply of power to the cache memory in accordance with the state of the prefetch when determined as idle state; and a power supply control unit that controls the power supply unit so as to stop the supply of power, or controls the power supply unit so as to continue the supply of power.
    Type: Application
    Filed: July 11, 2012
    Publication date: March 28, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusuke SHIROTA, Tetsuro KIMURA, Tatsunori KANAI, Haruhiko TOYAMA, Koichi FUJISAKI, Junichi SEGAWA, Masaya TARUI, Satoshi SHIRAI, Hiroyoshi HARUKI, Akihiro SHIBATA
  • Publication number: 20120246390
    Abstract: According to one embodiment, an information processing apparatus includes an auxiliary storage unit, a non-volatile main storage unit, a secondary cell, a first writing unit, and a second writing unit. The non-volatile main storage unit includes a cache area to temporarily store therein data that is to be stored in the auxiliary storage unit. The first writing unit writes the data into the cache area. The second writing unit writes the data written in the cache area into the auxiliary storage unit when an amount of power in the secondary cell is greater than a predetermined first threshold.
    Type: Application
    Filed: January 9, 2012
    Publication date: September 27, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsunori Kanai, Tetsuro Kimura, Haruhiko Toyama, Koichi Fujisaki, Hiroyoshi Haruki, Masaya Tarui, Satohi Shirai, Akihiro Shibata
  • Publication number: 20120246356
    Abstract: According to an embodiment, a control device includes a receiving unit configured to receive an interrupt request requesting an interrupt process to be executed by a processing device that executes one or more processes; a storage unit configured to store therein the interrupt request; a determining unit configured to determine a state of the processing device; a sending unit configured to send the interrupt request to the processing device; and a control unit configured to store the interrupt request received by the receiving unit in the storage unit when the processing device is determined by the determining unit to be in an idle state in which the processing device is not executing the processes and a predetermined condition is not satisfied, and to control the sending unit to send the interrupt request stored in the storage unit to the processing device when the predetermined condition is satisfied.
    Type: Application
    Filed: December 22, 2011
    Publication date: September 27, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihiro Shibata, Koichi Fujisaki, Tetsuro Kimura, Tatsunori Kanai, Haruhiko Toyama, Satoshi Shirai, Masaya Tarui, Hiroyoshi Haruki
  • Publication number: 20120246501
    Abstract: According to one embodiment, a controller includes a state detecting unit, a calculating unit, and a determining unit. The state detecting unit detects an idle state in which indicates there are no process that can execute on a processing device capable of performing one or more processes. The calculating unit calculates a resuming time, which indicates a time length until the next process starts, when the state detecting unit detects the idle state. The determining unit determines an operation mode of the processing device on the basis of the resuming time calculated by the calculating unit.
    Type: Application
    Filed: January 9, 2012
    Publication date: September 27, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyoshi Haruki, Koichi Fujisaki, Satoshi Shirai, Masaya Tarui, Akihiro Shibata, Tetsuro Kimura, Tatsunori Kanai, Haruhiko Toyama
  • Publication number: 20120246503
    Abstract: According to one embodiment, an information processing apparatus includes a processor, a non-volatile storage unit, a receiving unit, a judging unit, and a transmitting unit. The receiving unit receives from the processor an inquiry about accessibility of the storage unit. The judging unit judges, upon receipt of the inquiry, whether the storage unit is accessible on the basis of a start-up time period between starting power supply to the storage unit and activation of the storage unit. The transmitting unit transmits a judgment result obtained by the judging unit to the processor.
    Type: Application
    Filed: March 15, 2012
    Publication date: September 27, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi Fujisaki, Tatsunori Kanai, Tetsuro Kimura, Haruhiko Toyama, Satoshi Shirai, Masaya Tarui, Hiroyoshi Haruki, Akihiro Shibata
  • Patent number: 8191155
    Abstract: A microprocessor having a processor core includes an information acquisition unit that acquires information encrypted to be used by the processor core, from outside; a decryption unit that decrypts the information with a symmetric key to obtain plain text; and a controller that controls processing on the information acquired by the information acquisition unit based on the symmetric key.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: May 29, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyoshi Haruki, Mikio Hashimoto, Takeshi Kawabata
  • Publication number: 20120079283
    Abstract: According to an embodiment, a memory management device increments a lower value of a first counter, updates the counter by incrementing an upper value and resetting the lower value when the lower value overflows, increments to update the lower counter value when the upper value is incremented as a result of writing a second data piece having the upper value in common to a memory, recalculates a first secret value calculated using the first counter values and a root secret value in response to the first counter update, writes a first data piece and the first secret value to the memory, and at reading of the first data piece and the first secret value, calculates a second secret value using the updated first counter values and the root secret value, and compares the first secret value with the second secret value to verify the first data piece.
    Type: Application
    Filed: September 1, 2011
    Publication date: March 29, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mikio HASHIMOTO, Hiroyoshi HARUKI, Takeshi KAWABATA, Tomohide JOKAN, Yurie FUJIMATSU, Ryotaro HAYASHI, Fukutomo NAKANISHI
  • Publication number: 20120066770
    Abstract: According to one embodiment, there is provided a an information processing apparatus, including: a program acceptance portion; a program storage portion; a first function type storage portion; a function type extraction portion; a second function type storage portion; a first alternate function type storage portion; an alternate function type extraction portion; a second alternate function type storage portion; a selection portion; a judging portion; an updating portion; and a protection attribute determination portion.
    Type: Application
    Filed: August 3, 2011
    Publication date: March 15, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryotaro HAYASHI, Fukutomo NAKANISHI, Mikio HASHIMOTO, Hiroyoshi HARUKI, Yurie FUJIMATSU
  • Publication number: 20110296192
    Abstract: According to one embodiment, an information processing device stores a program list and plural types of security functions each defining therein protection attributes for respective arguments related to input and output of data to be protected, and stores function argument protection attributes and dependency relations each of which is defined by a determinant set and a dependent attribute that satisfy a predetermined condition.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 1, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryotaro HAYASHI, Mikio Hashimoto, Hiroyoshi Haruki, Yurie Fujimatsu
  • Publication number: 20110107336
    Abstract: A microprocessor executes programs in a pipeline architecture that includes a task register management unit that switches a value of a task register to second register information that is used when a second task is executed after the execution of a first task is completed, if a switch instruction to the second task is issued when a plurality of units executes the first task, and a task manager that switches a value of a task identification information register to a second task identifier after the value is switched to the second register information, and grants each of the plurality of units permission to execute the second task.
    Type: Application
    Filed: November 4, 2010
    Publication date: May 5, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyoshi Haruki, Mikio Hashimoto, Takeshi Kawabata
  • Patent number: 7853954
    Abstract: A microprocessor executes programs in a pipeline architecture including a task register management unit that, if a switch instruction to a second task is issued when a plurality of units executes a first task, switches a value of a task register to second register information that is used when the second task is executed after the execution of the first task is completed and a task manager that switches a value of a task identification information register to a second task identifier after the value is switched to the second register information, and grants each of the plurality of units permission to execute the second task.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: December 14, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyoshi Haruki, Mikio Hashimoto, Takeshi Kawabata
  • Patent number: 7707645
    Abstract: A microprocessor includes a decryption unit that decrypts information to be utilized by a processor core to obtain plaintext information when the acquired information is encrypted; and a plaintext information storing unit that stores the plaintext information. The microprocessor also includes a protected attribute adding unit that adds a protected attribute indicating one of protection and non-protection to the plaintext information based on whether the decryption has been performed; an access request acquiring unit that acquires an access request to the plaintext information; a request type identifying unit that identifies a type of request of the access request; and an access controlling unit that controls an access to the plaintext information based on the type of request and the protected attribute.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: April 27, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyoshi Haruki, Mikio Hashimoto, Takeshi Kawabata
  • Patent number: 7603566
    Abstract: A microprocessor includes a first information holding unit, a second information holding unit, and a switching authorization unit. The first information holding unit holds process identification information and authentication information which are associated with each other. The second information holding unit denies access from outside, and holds entry information of a process and the authentication information which are associated with each other. The switching authorization unit allows switching process when the authentication information held in the first information holding unit with the authentication information held in the second information holding unit match.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: October 13, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mikio Hashimoto, Hiroyoshi Haruki
  • Publication number: 20090138729
    Abstract: A first storage unit stores a plurality of security functions each defining a first protection attribute requiring a storage of a value of an argument for input/output of data. A second storage unit stores a program list describing a second protection attribute of a variable indicating a storage area of the data and an executing procedure of a predetermined process. An identifying unit identifies a third protection attribute of an actual argument for input/output of a security function based on the second protection attribute. When a judging unit judges not all of third protection attributes match with first protection attributes, an output unit outputs error information indicating a mismatch of the protection attributes.
    Type: Application
    Filed: November 19, 2008
    Publication date: May 28, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mikio Hashimoto, Hiroyoshi Haruki, Yurie Fujimatsu, Takeshi Kawabata
  • Publication number: 20060010308
    Abstract: A microprocessor executes programs in a pipeline architecture that includes a task register management unit that switches a value of a task register to second register information that is used when a second task is executed after the execution of a first task is completed, if a switch instruction to the second task is issued when a plurality of units executes the first task, and a task manager that switches a value of a task identification information register to a second task identifier after the value is switched to the second register information, and grants each of the plurality of units permission to execute the second task.
    Type: Application
    Filed: July 7, 2005
    Publication date: January 12, 2006
    Inventors: Hiroyoshi Haruki, Mikio Hashimoto, Takeshi Kawabata
  • Publication number: 20060005260
    Abstract: A microprocessor includes a decryption unit that decrypts information to be utilized by a processor core to obtain plaintext information when the acquired information is encrypted; and a plaintext information storing unit that stores the plaintext information. The microprocessor also includes a protected attribute adding unit that adds a protected attribute indicating one of protection and non-protection to the plaintext information based on whether the decryption has been performed; an access request acquiring unit that acquires an access request to the plaintext information; a request type identifying unit that identifies a type of request of the access request; and an access controlling unit that controls an access to the plaintext information based on the type of request and the protected attribute.
    Type: Application
    Filed: June 23, 2005
    Publication date: January 5, 2006
    Inventors: Hiroyoshi Haruki, Mikio Hashimoto, Takeshi Kawabata