Abstract: An electronic preview guide (EPG) display apparatus for use in a broadcast receiver, for selectively presenting viewers a broadcast schedule. The broadcast schedule is presented in a grid pattern with one or more rows each showing a TV channel number or a TV station name and an array of slots containing preview guide messages of its broadcast schedule extending in the direction of time axis, using a preview guide data broadcast by each broadcast station and a present time. The apparatus includes a display controller for making an EPG slot at the present time or a viewer-designated time wider than other slots within the EPG screen.

Abstract: A television system includes a television and an external media module. The television includes a television control unit capable of generating a control signal, apparatus for receiving a video signal, a media controller for generating a graphics signal, and a display unit for displaying either the video signal or a combined video and graphics signal. The external media module, external to the television, is connectable via an interface with the media controller, and performs a graphics on-screen display application in accordance with the television control signal.

Abstract: Time series signals are recognized by extracting a multiplicity of candidate feature vectors characterizing an individual time series signal without fixing a boundary for the individual time series signal, and calculating similarity values for each of the multiplicity of candidate feature vectors and the reference patterns stored in the recognition dictionary, from which one reference pattern for which the similarity value is greater than a prescribed threshold value is selected as a recognition result. New reference patterns to be stored in the recognition dictionary are learned by artificially synthesizing signal patterns with variations for learning; extracting feature vectors for learning from the recognition results and the similarity values obtained by the recognizing step from the signal patterns with variations for learning; and obtaining new reference patterns from the feature vectors for learning extracted by the extracting step.

Abstract: An NTSC tuner, an ISDB tuner, a CATV tuner, and a CATV modulator are connected to an analog switch box. Demodulation sections, an A/D, clock-reproducing section, and a modulation section are connected between the analog switch box a bus. MPEG2 video decoder sections, an MPEG2 audio decoder sections, an NTSC/EDTV horizontal decoder section, an EDTV vertical decoder section, an MPEG2 video encoder section, and an MPEG2 audio encoder section are connected between the bus and a bus. An audio amplifier, a graphics controller, and A/D conversion sections are connected the bus. The switch box and the buses are connected to a bus controller, which is connected to a CPU, a memory, and a remote-control I/F. These modules are selectively used to receive and process digital broadcasting signals, digital CATV signals or NTSC broadcasting signals.

Abstract: A time series signal recognition capable of obtaining a high recognition rate even for the speech data with low S/N ratio in noisy environments. The time series signals are recognized by extracting a plurality of candidate feature vectors characterizing an individual time series signal, without fixing a boundary for the individual time series signal. Similarity values are calculated for each of the plurality of candidate feature vectors and the reference patterns stored in the recognition dictionary, from which one reference pattern for which the similarity value is greater than a prescribed threshold value is selected as a recognition result. New reference patterns to be stored in the recognition dictionary are learned by acquiring actual background noise of the apparatus, and mixing prescribed noiseless signal patterns with the acquired background noise to form signal patterns for learning.

Abstract: In a scanning line converting operation, an image signal is processed through a system including memories, switches, arithmetic circuits, an adder, a subtracter and a switch. In a graphic process, coordinate data processed by a parameter generator and a drawing unit is subjected to a coordinate converting calculation by the arithmetic circuits and supplied to an address generator. Based on an address generated by the address generator, a texture model, which has been stored in a memory under control of a CPU, is read out and supplied to a synthesizing circuit. In the synthesizing circuit, the texture model is attached to a polygon output from a drawing unit.

Abstract: The horizontal processing circuits subject the image data input respectively to the compression processing or the expansion processing in the horizontal direction and output said processed image data. The transfer means composed of the bus controller 338 and the bus 333 transfers respective image data from the horizontal processing circuits time-divisionally. The vertical processing circuit 334 subjects the respective transferred image data to the compression processing or the expansion processing in the vertical direction time-divisionally. The post-processing circuit 335 and the display device 464 display the image data from the vertical processing circuit 334.

Abstract: Texture mapping is performed on polygons at the same speed as a polygon drafting process without a texture cache, thereby reducing complexity without an increase in cost. An image memory is constituted in a double-buffer structure, and an address line, a data line and a memory control line are individually connected to each buffer. One of the two buffers is used for texture data, and the other for a drawing result. The texture data is one-dimensional, and the size thereof is less than a maximum value of a column address. The other buffer is an imaginary double buffer with two buffers, one of the buffers being used for reading out image data from a SAM port, the other being used for writing image data produced from polygons. Read/write switching is effected in a vertical flyback period. In the read-out buffer, just after row-directional read-out, the associated row is cleared by the flash write function of a multiport DRAM in a horizontal flyback period, and the next read-out address is output.