Patents by Inventor Hiroyuki Fukumizu

Hiroyuki Fukumizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210062337
    Abstract: An exhaust pipe device according to an embodiment includes a pipe body; a dielectric formed in an annular and disposed along an inner wall of the pipe body; an internal electrode formed in an annular, disposed along an inner wall of the dielectric with a part of an inner wall surface of the dielectric left and configured to expose the part of the inner wall surface of the dielectric left without being disposed to a center side of the pipe body; and a plasma generation circuit configured to generate plasma on an exposed surface of the dielectric by using the internal electrode, wherein the exhaust pipe device functions as a part of an exhaust pipe disposed between a film forming chamber and a vacuum pump for exhausting an inside of the film forming chamber.
    Type: Application
    Filed: February 4, 2020
    Publication date: March 4, 2021
    Applicant: Kioxia Corporation
    Inventors: Hiroshi MATSUBA, Akihiro OISHI, Kazuaki KURIHARA, Hiroyuki FUKUMIZU
  • Publication number: 20200075297
    Abstract: An exhaust pipe device according to an embodiment includes a pipe body; an internal electrode disposed in the pipe body; and a plasma generation circuit configured to generate plasma in the pipe body by using the internal electrode, wherein the exhaust pipe device is used as a part of an exhaust pipe disposed between a film forming chamber and a vacuum pump for exhausting an inside of the film forming chamber.
    Type: Application
    Filed: March 4, 2019
    Publication date: March 5, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Akihiro OISHI, Hiroyuki FUKUMIZU, Hiroshi MATSUBA, Kazuaki KURIHARA, Takeshi YAMAUCHI
  • Patent number: 10181561
    Abstract: According to one embodiment, a memory device includes a stacked body. The stacked body includes first and second electrodes, and an oxide layer provided between the first and second electrodes. The second electrode includes a semiconductor layer, and a metal-containing region including at least one of first or second metallic element and being provided between at least a portion of the semiconductor layer and at least a portion of the oxide layer. The first metallic element includes at least one selected from Pt, Pd, Ir, Ru, Re, and Os. The second metallic element includes at least one selected Ti, W, Mo, and Ta. The stacked body has first and second states. The first state is obtained by causing a current to flow in the stacked body from the second toward first electrode. The second state is obtained by causing a current to flow from the first toward second electrode.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: January 15, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyuki Fukumizu, Takeshi Yamaguchi
  • Publication number: 20180076597
    Abstract: A quantum cascade laser device includes a substrate, a semiconductor stacked body and a first electrode. The semiconductor stacked body includes an active layer and a first clad layer. The active layer is configured to emit infrared laser light by an intersubband optical transition. A ridge waveguide is provided in the semiconductor stacked body. A distributed feedback region is provided along a first straight line. The ridge waveguide extends along the first straight line. The first electrode is provided at an upper surface of the distributed feedback region. A diffraction grating is arranged along the first straight line. The distributed feedback region includes a an increasing region where a length of the diffraction grating along a direction orthogonal to the first straight line increases from one end portion of the distributed feedback region toward another end portion of the distributed feedback region.
    Type: Application
    Filed: August 24, 2017
    Publication date: March 15, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki FUKUMIZU, Tsutomu Kakuno
  • Publication number: 20180013061
    Abstract: According to one embodiment, a memory device includes a stacked body. The stacked body includes first and second electrodes, and an oxide layer provided between the first and second electrodes. The second electrode includes a semiconductor layer, and a metal-containing region including at least one of first or second metallic element and being provided between at least a portion of the semiconductor layer and at least a portion of the oxide layer. The first metallic element includes at least one selected from Pt, Pd, Ir, Ru, Re, and Os. The second metallic element includes at least one selected Ti, W, Mo, and Ta. The stacked body has first and second states. The first state is obtained by causing a current to flow in the stacked body from the second toward first electrode. The second state is obtained by causing a current to flow from the first toward second electrode.
    Type: Application
    Filed: July 7, 2017
    Publication date: January 11, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Hiroyuki FUKUMIZU, Takeshi YAMAGUCHI
  • Patent number: 9679947
    Abstract: A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: June 13, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaki Yamato, Yasuhiro Nojiri, Shigeki Kobayashi, Hiroyuki Fukumizu, Takeshi Yamaguchi
  • Publication number: 20170133586
    Abstract: A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.
    Type: Application
    Filed: January 23, 2017
    Publication date: May 11, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaki YAMATO, Yasuhiro NOJIRI, Shigeki KOBAYASHI, Hiroyuki FUKUMIZU, Takeshi YAMAGUCHI
  • Patent number: 9590016
    Abstract: A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: March 7, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaki Yamato, Yasuhiro Nojiri, Shigeki Kobayashi, Hiroyuki Fukumizu, Takeshi Yamaguchi
  • Publication number: 20160099289
    Abstract: A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.
    Type: Application
    Filed: December 11, 2015
    Publication date: April 7, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaki YAMATO, Yasuhiro Nojiri, Shigeki Kobayashi, Hiroyuki Fukumizu, Takeshi Yamaguchi
  • Patent number: 9252358
    Abstract: First, a trench penetrating first conductive layers and interlayer insulating layers is formed. Next, a column-shaped conductive layer is formed to fill the trench via a side wall layer. Then, after formation of the side wall layer, by migration of oxygen atoms between the side wall layer and the first conductive layers or migration of oxygen atoms between the side wall layer and the interlayer insulating layers, a proportion of oxygen atoms in the side wall layer adjacent to the interlayer insulating layers is made larger than a proportion of oxygen atoms in the side wall layer adjacent to the first conductive layers, whereby the side wall layer adjacent to the first conductive layers is caused to function as the variable resistance element.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: February 2, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Kanno, Takayuki Tsukamoto, Hiroyuki Fukumizu, Yoichi Minemura, Takamasa Okawa
  • Publication number: 20160027682
    Abstract: According to the embodiments, a manufacturing method for a semiconductor device includes forming recessed parts on a surface of a semiconductor layer. The manufacturing method for the semiconductor device includes a process for forming a buffer layer, which has a melting point lower than that of the semiconductor layer, on a surface of the recessed part on the surface of the semiconductor layer. The manufacturing method for the semiconductor device includes a process for forming a high-melting point film, which has the melting point higher than that of the semiconductor layer, on the buffer layer and fills the recessed part with the high-melting point film. The manufacturing method for the semiconductor device includes a process for heating the semiconductor layer having the buffer layer and the high-melting point film formed thereon at a temperature equal to or higher than the melting point of the buffer layer.
    Type: Application
    Filed: March 2, 2015
    Publication date: January 28, 2016
    Inventors: Shintaro Okujo, Kenichi Yoshino, Hiroyuki Fukumizu, Satoshi Kato
  • Patent number: 9246088
    Abstract: A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: January 26, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaki Yamato, Yasuhiro Nojiri, Shigeki Kobayashi, Hiroyuki Fukumizu, Takeshi Yamaguchi
  • Publication number: 20160020232
    Abstract: According to one embodiment, a solid state imaging device includes a semiconductor layer and an anti-reflection film. The semiconductor layer performs photoelectric conversion. The anti-reflection film is provided on the semiconductor layer. The anti-reflection film is conductive.
    Type: Application
    Filed: July 13, 2015
    Publication date: January 21, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyuki FUKUMIZU, Rikyu IKARIYAMA
  • Patent number: 9219175
    Abstract: According to one embodiment, an imaging device includes a semiconductor layer, an electrode, first and second insulating films, and a light blocking film. The semiconductor layer has a first surface and a second surface on an opposite side to the first surface, and includes pixels configured to detect light. The electrode is provided on the first surface and is configured to control an output of the pixels. The first insulating film is provided on the second surface. The second insulating film is provided on the first insulating film and has a smaller refractive index in a visible light range than the first insulating film. One end of the light blocking film is located in the second insulating film or at a same level as a surface of the second insulating film. Another end of the light blocking film is located in the semiconductor layer.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: December 22, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Fukumizu, Takaaki Minami, Kentaro Eda, Takeshi Yosho
  • Publication number: 20150357359
    Abstract: According to one embodiment, a solid state imaging device includes a semiconductor layer, an intermediate film, an anti-reflection film and a conductive film. The semiconductor layer performs photoelectric conversion. The intermediate film is provided on the semiconductor layer. The intermediate film has a negative charge. The anti-reflection film is provided on the intermediate film. The conductive film is provided on the anti-reflection film.
    Type: Application
    Filed: June 4, 2015
    Publication date: December 10, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Rikyu IKARIYAMA, Hiroyuki FUKUMIZU
  • Publication number: 20150279877
    Abstract: According to one embodiment, a solid state imaging device includes a semiconductor layer, a first layer, a second layer and third layer. The semiconductor layer performs photoelectric conversion. The first layer has a first refractive index. The second layer is provided between the first layer and the semiconductor layer, the second layer includes a metal oxide and has a second refractive index not greater than the first refractive index. The third layer is provided between the first layer and the second layer. The third layer has a third refractive index and includes an element bonding covalently with oxygen. The third refractive index is not greater than the first refractive index.
    Type: Application
    Filed: February 19, 2015
    Publication date: October 1, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Rikyu IKARIYAMA, Hiroyuki FUKUMIZU, Noriteru YAMADA, Naohiro TSUDA, Kazunori KAKEHI
  • Publication number: 20150255665
    Abstract: According to one embodiment, a laser heating treatment method includes forming a film having a higher melting point than a structural body provided on a substrate so as to cover the structural body, and heating the structural body by irradiating the film and the structural body with laser.
    Type: Application
    Filed: February 25, 2015
    Publication date: September 10, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki FUKUMIZU, Yoshio Kasai, Takaaki Minami, Kenichi Yoshino, Yosuke Kitamura, Yusaku Konno, Koichi Kawamura, Satoshi Kato, Naoaki Sakurai
  • Publication number: 20150115388
    Abstract: A solid-state imaging device includes a plurality of photoelectric transducers disposed in an array in a semiconductor layer. Each photoelectric transducer includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type. The first and second regions are in direct contact. An isolation region is between each adjacent pair of photoelectric transducers. The isolation region includes an insulating material extending from a surface of the semiconductor layer and a third semiconductor region of the first conductivity type surrounding the insulating material. The third semiconductor region is between the insulating material and the first semiconductor region, and the first semiconductor region is between the second and third semiconductor regions.
    Type: Application
    Filed: October 24, 2014
    Publication date: April 30, 2015
    Inventors: Kentaro EDA, Kenichi YOSHINO, Shintaro OKUJO, Hiroyuki FUKUMIZU, Takaaki MINAMI, Takeshi YOUSYOU, Hiroaki ASHIDATE
  • Patent number: 9018613
    Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; and a memory cell block formed on the semiconductor substrate and configured having a plurality of memory cell arrays, each of the memory cell arrays including a plurality of column lines, a plurality of row lines, and a plurality of memory cells disposed at each of intersections of the plurality of column lines and the plurality of row lines, each of the memory cells including a variable resistance element having a transition metal oxide as a material, at least one of the plurality of column lines and the plurality of row lines being a polysilicon wiring line having polysilicon as a material, and the memory cell block including a block film between the variable resistance element of the memory cell and the polysilicon wiring line.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: April 28, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Nojiri, Hiroyuki Fukumizu, Shigeki Kobayashi, Masaki Yamato
  • Patent number: 9013912
    Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory layers; and a control unit configured to control a voltage applied to the memory cell array. Each of the memory layers comprises a first line and a second line, and further includes a memory cell disposed between the first line and the second line and including a variable resistance element. The control unit is configured to, when executing a forming operation on the memory cell array, execute the forming operation sequentially on the plurality of memory layers. The forming operation is executed sequentially on the memory layers in ascending order of a magnitude of a non-selected current flowing in a non-selected memory cell during the forming operation.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Nojiri, Shigeki Kobayashi, Masaki Yamato, Hiroyuki Fukumizu