Patents by Inventor Hiroyuki HANAZONO

Hiroyuki HANAZONO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10141217
    Abstract: The present invention is to provide a dicing-tape integrated film for the backside of a semiconductor that is capable of suppressing the increase of the peel strength between the dicing tape and the film for the backside of a flip-chip semiconductor due to heating. The dicing-tape integrated film for the backside of a semiconductor has a dicing tape having a substrate and a pressure-sensitive adhesive layer formed on the substrate and a film for the backside of a flip-chip semiconductor formed on the pressure-sensitive adhesive layer of the dicing tape, in which the difference (?2??1) of the surface free energy ?2 and the surface free energy ?1 is 10 mJ/m2 or more, where ?1 represents the surface free energy of the pressure-sensitive adhesive layer and ?2 represents the surface free energy of the film for the backside of a flip-chip semiconductor.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: November 27, 2018
    Assignee: NITTO DENKO CORPORATION
    Inventors: Naohide Takamoto, Hiroyuki Hanazono, Akihiro Fukui
  • Patent number: 10014235
    Abstract: An underfill material having sufficient curing reactivity, and capable of achieving a small change in viscosity and good electrical connection even when loaded with thermal history, a laminated sheet including the underfill material, and a method for manufacturing a semiconductor device. The underfill material has a melt viscosity at 150° C. before heating treatment of 50 Pa·s or more and 3,000 Pa·s or less, a viscosity change rate of 500% or less, at 150° C. as a result of the heating treatment, and a reaction rate represented by {(Qt?Qh)/Qt}×100% of 90% or more, where Qt is a total calorific value in a process of temperature rise from ?50° C. to 300° C. and Qh is a total calorific value in a process of temperature rise from ?50° C. to 300° C. after heating at 175° C. for 2 hours in a DSC measurement.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: July 3, 2018
    Assignee: NITTO DENKO CORPORATION
    Inventors: Naohide Takamoto, Hiroyuki Hanazono, Akihiro Fukui
  • Patent number: 9679797
    Abstract: The present invention is to provide a dicing-tape integrated film for the backside of a semiconductor that is capable of suppressing the transfer of the coloring agent contained in a film for the backside of a flip-chip semiconductor formed on the pressure-sensitive adhesive layer of the dicing tape onto the dicing tape. The dicing-tape integrated film for the backside of a semiconductor has a dicing tape having a substrate and a pressure-sensitive adhesive layer formed on the substrate and a film for the backside of a flip-chip semiconductor formed on the pressure-sensitive adhesive layer of the dicing tape, the film for the backside of a flip-chip semiconductor contains a coloring agent, and the solubility of the coloring agent to toluene at 23° C. is 2 g/100 ml or less.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: June 13, 2017
    Assignee: NITTO DENKO CORPORATION
    Inventors: Naohide Takamoto, Hiroyuki Hanazono, Akihiro Fukui
  • Publication number: 20170018472
    Abstract: An underfill material having sufficient curing reactivity, and capable of achieving a small change in viscosity and good electrical connection even when loaded with thermal history, a laminated sheet including the underfill material, and a method for manufacturing a semiconductor device. The underfill material has a melt viscosity at 150° C. before heating treatment of 50 Pa·s or more and 3,000 Pa·s or less, a viscosity change rate of 500% or less, at 150° C. as a result of the heating treatment, and a reaction rate represented by {(Qt?Qh)/Qt}×100% of 90% or more, where Qt is a total calorific value in a process of temperature rise from ?50° C. to 300° C. and Qh is a total calorific value in a process of temperature rise from ?50° C. to 300° C. after heating at 175° C. for 2 hours in a DSC measurement.
    Type: Application
    Filed: February 20, 2015
    Publication date: January 19, 2017
    Inventors: Naohide Takamoto, Hiroyuki Hanazono, Akihiro Fukui
  • Publication number: 20160240394
    Abstract: A method for producing a semiconductor device includes: a Step A of preparing a chip with sheet-shaped resin composition in which a sheet-shaped resin composition is pasted onto a bump formation surface of a semiconductor chip, a Step B of preparing a substrate for mounting on which an electrode is formed, a Step C of pasting the chip with resin composition to the substrate for mounting so that the resin composition serves as a pasting surface with the bump formed on the semiconductor chip facing toward the electrode formed on the substrate for mounting, a Step D of heating the resin composition to semi-cure the resin composition after the Step C, and a Step E of heating the resin composition at a higher temperature than that in the Step D to cure the resin composition after the Step D while bonding the bump and the electrode.
    Type: Application
    Filed: September 19, 2014
    Publication date: August 18, 2016
    Applicant: NITTO DENKO CORPORATION
    Inventors: Akihiro Fukui, Naohide Takamoto, Hiroyuki Hanazono
  • Publication number: 20160240523
    Abstract: Provided is a method for manufacturing a semiconductor device, which can manufacture a semiconductor device at a high yield ratio by suppressing dissolution of a sheet-shaped resin composition when cleaning a wafer after peeling a supporting member from the wafer.
    Type: Application
    Filed: October 3, 2014
    Publication date: August 18, 2016
    Inventors: Naohide Takamoto, Hiroyuki Hanazono, Akihiro Fukui
  • Publication number: 20160233184
    Abstract: A method for manufacturing a semiconductor includes: a Step A of preparing a chip with sheet-shaped resin composition in which a sheet-shaped resin composition is pasted onto a semiconductor chip, a Step B of preparing an adherend, a Step C of pasting the chip with sheet-shaped resin composition onto the adherend so that the sheet-shaped resin composition serves as a pasting surface, a Step D of heating the sheet-shaped resin composition to semi-cure the sheet-shaped resin composition after the Step C, and a Step E of heating the sheet-shaped resin composition at a higher temperature than in the Step D to cure the sheet-shaped resin composition after the Step D.
    Type: Application
    Filed: September 19, 2014
    Publication date: August 11, 2016
    Applicant: Nitto Denko Corporation
    Inventors: Hiroyuki Hanazono, Naohide Takamoto, Akihiro Fukui
  • Patent number: 9366815
    Abstract: An opto-electric hybrid board which is excellent in the mountability of an optical element and in flexibility is provided. The opto-electric hybrid board includes an electric circuit board, an optical waveguide, and metal layers. The electric circuit board includes an insulative layer having front and back surfaces, and optical element mounting pads formed on the front surface of the insulative layer. The optical waveguide includes a first cladding layer, and is formed on the back surface of the insulative layer of the electric circuit board in such a manner that the first cladding layer is in contact with the back surface of the insulative layer. The metal layers are provided between the insulative layer and the first cladding layer and disposed in corresponding relation to the optical element mounting pads.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: June 14, 2016
    Assignee: NITTO DENKO CORPORATION
    Inventors: Hiroyuki Hanazono, Yuichi Tsujita
  • Publication number: 20160075871
    Abstract: Provided are a thermosetting resin composition with which a semiconductor device having a high connection reliability can be provided while securing availability of member materials by reducing a difference in thermal-responsive behavior between a semiconductor element and an adherend, and a method for producing a semiconductor device using the thermosetting resin composition. The present invention provides a thermosetting resin composition for producing a semiconductor device, the thermosetting resin composition comprising: an epoxy resin; and a novolak-type phenol resin having a hydroxyl equivalent of 200 g/eq or more.
    Type: Application
    Filed: April 11, 2014
    Publication date: March 17, 2016
    Inventors: Kosuke Morita, Naohide Takamoto, Hiroyuki Hanazono, Akihiro Fukui
  • Patent number: 9288903
    Abstract: A plurality of conductor traces are formed on a porous base insulating layer made of porous ePTFE. Each conductor trace has a laminated structure of a seed layer and a conductor layer. A cover insulating layer is formed on the base insulating layer to cover each conductor trace. The ePTFE used as the porous base insulating layer has continuous pores. An average pore size of the ePTFE is not less than 0.05 ?m and not more than 1.0 ?m.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: March 15, 2016
    Assignee: NITTO DENKO CORPORATION
    Inventors: Mineyoshi Hasegawa, Keisuke Okumura, Shinichi Inoue, Hiroyuki Hanazono
  • Publication number: 20160040045
    Abstract: The present invention provides an adhesive film for underfill that is capable of increasing a glass transition temperature without losing flexibility. The present invention relates to an adhesive film for underfill containing resin components containing an epoxy resin having a number average molecular weight of 600 or less, a phenol resin having a number average molecular weight exceeding 500, and an elastomer in which a content of the epoxy resin in the resin components is 5 to 50% by weight, and the content of the phenol resin in the resin components is 5 to 50% by weight.
    Type: Application
    Filed: March 27, 2014
    Publication date: February 11, 2016
    Inventors: Kosuke Morita, Naohide Takamoto, Hiroyuki Hanazono, Akihiro Fukui
  • Publication number: 20160035640
    Abstract: The present invention provides an underfill film and a sealing sheet that are excellent in thermal conductive property and are capable of satisfactorily filling the space between the semiconductor element and the substrate. The present invention relates to an underfill film having a resin and a thermally conductive filler, in which a content of the thermally conductive filler is 50% by volume or more, an average particle size of the thermally conductive filler is 30% or less of a thickness of the underfill film, and a maximum particle size of the thermally conductive filler is 80% or less of the thickness of the underfill film.
    Type: Application
    Filed: March 27, 2014
    Publication date: February 4, 2016
    Inventors: Kosuke MORITA, Naohide TAKAMOTO, Hiroyuki HANAZONO, Akihiro FUKUI
  • Publication number: 20160013089
    Abstract: A production method for a semiconductor device is provided whereby, when peeling a support body from an attached wafer, melting of a sheet-shaped resin composition pasted to the other surface of the wafer can be suppressed. The method comprises: preparing a support body-attached wafer, said support body-attached wafer having the support body bonded, via a temporary fixing layer, to one surface of the wafer having a through electrode formed therein; preparing a dicing tape-integrated sheet-shaped resin composition having a sheet-shaped resin composition having an external shape smaller than the other surface of the wafer formed upon a dicing tape; pasting the other surface of the support body-attached wafer to the sheet-shaped resin composition in the dicing tape-integrated sheet-shaped resin composition; and melting the temporary fixing layer by a solvent and peeling the support body away from the wafer.
    Type: Application
    Filed: February 28, 2014
    Publication date: January 14, 2016
    Inventors: Naohide Takamoto, Kosuke Morita, Akihiro Fukui, Hiroyuki Hanazono, Akira Suzuki
  • Publication number: 20150380277
    Abstract: An object of the present invention is to provide an underfill sheet that enables suitable filling of unevenness of a circuit surface of a semiconductor element, a suitable connection of a terminal of the semiconductor element and a terminal of an adherend, and suppression of outgas. The present invention relates to the underfill sheet having a viscosity of 1,000 Pa·s to 10,000 Pa·s at 150° C. and 0.05 to 0.20 rotations/min; and a minimum viscosity of 100 Pa·s or more at 100 to 200° C. and 0.3 to 0.7 rotations/min.
    Type: Application
    Filed: February 7, 2014
    Publication date: December 31, 2015
    Applicant: NITTO DENKO CORPORATION
    Inventors: Kosuke Morita, Naohide Takamoto, Hiroyuki Hanazono, Akihiro Fukui
  • Publication number: 20150364357
    Abstract: The present invention is to provide a dicing-tape integrated film for the backside of a semiconductor that is capable of suppressing the increase of the peel strength between the dicing tape and the film for the backside of a flip-chip semiconductor due to heating. The dicing-tape integrated film for the backside of a semiconductor has a dicing tape having a substrate and a pressure-sensitive adhesive layer formed on the substrate and a film for the backside of a flip-chip semiconductor formed on the pressure-sensitive adhesive layer of the dicing tape, in which the difference (?2??1) of the surface free energy ?2 and the surface free energy ?1 is 10 mJ/m2 or more, where ?1 represents the surface free energy of the pressure-sensitive adhesive layer and ?2 represents the surface free energy of the film for the backside of a flip-chip semiconductor.
    Type: Application
    Filed: May 13, 2015
    Publication date: December 17, 2015
    Applicant: NITTO DENKO CORPORATION
    Inventors: Naohide TAKAMOTO, Hiroyuki HANAZONO, Akihiro FUKUI
  • Publication number: 20150357223
    Abstract: The present invention is to provide a dicing-tape integrated film for the backside of a semiconductor that is capable of suppressing the transfer of the coloring agent contained in a film for the backside of a flip-chip semiconductor formed on the pressure-sensitive adhesive layer of the dicing tape onto the dicing tape. The dicing-tape integrated film for the backside of a semiconductor has a dicing tape having a substrate and a pressure-sensitive adhesive layer formed on the substrate and a film for the backside of a flip-chip semiconductor formed on the pressure-sensitive adhesive layer of the dicing tape, the film for the backside of a flip-chip semiconductor contains a coloring agent, and the solubility of the coloring agent to toluene at 23° C. is 2 g/100 ml or less.
    Type: Application
    Filed: May 12, 2015
    Publication date: December 10, 2015
    Applicant: NITTO DENKO CORPORATION
    Inventors: Naohide TAKAMOTO, Hiroyuki HANAZONO, Akihiro FUKUI
  • Patent number: 8837874
    Abstract: An opto-electric hybrid board capable of suppressing the increase in light propagation losses and excellent in flexibility, and a method of manufacturing the same, are provided. The opto-electric hybrid board includes an electric circuit board, an optical waveguide, and a metal layer. The electric circuit board includes an insulative layer having front and back surfaces, and electrical interconnect lines formed on the front surface of the insulative layer. The optical waveguide is formed on the back surface of the insulative layer. The metal layer is formed between the cladding layer and the insulative layer. At least part of the metal layer is formed in one of first and second patterns. The first pattern includes a distribution of dot-shaped protrusions, and the second pattern includes a distribution of dot-shaped recesses. A first cladding layer fills a site where the metal layer is removed by the patterning.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: September 16, 2014
    Assignee: Nitto Denko Corporation
    Inventors: Yuichi Tsujita, Yasuto Ishimaru, Hiroyuki Hanazono, Naoyuki Tanaka, Yasufumi Yamamoto, Shotaro Masuda, Mayu Ozaki
  • Patent number: 8822834
    Abstract: A printed circuit board includes a base insulating layer formed of a porous film. Conductor traces are formed on the base insulating layer formed of the porous film. A cover insulating layer is formed on the base insulating layer to cover the conductor traces. The porous film used as the base insulating layer has a reflectivity of not less than 50% for light of at least a part of wavelengths in a wavelength region from 400 nm to 800 nm.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: September 2, 2014
    Assignee: Nitto Denko Corporation
    Inventors: Shinichi Inoue, Hiroyuki Hanazono, Mineyoshi Hasegawa
  • Patent number: 8776579
    Abstract: A substance detection sensor includes an insulating layer; two electrodes spaced in opposed relation to each other on the insulating layer; and conductive layers formed between the two electrodes on the insulating layer so as to electrically connect the two electrodes, and of which a swelling ratio varies depending on the type and/or amount of a specific gas. The conductive layers are formed by dividing into plural layers between the two electrodes.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: July 15, 2014
    Assignee: Nitto Denko Corporation
    Inventors: Hiroshi Yamazaki, Toshiki Naito, Hiroyuki Hanazono
  • Patent number: 8768114
    Abstract: An opto-electric hybrid board which is capable of suppressing the increase in light propagation losses and which is excellent in flexibility, and a method of manufacturing the same are provided. The opto-electric hybrid board includes an electric circuit board, an optical waveguide, and a metal layer. The electric circuit board includes an insulative layer having front and back surfaces, and electrical interconnect lines formed on the front surface of the insulative layer. The optical waveguide is formed on the back surface of the insulative layer of the electric circuit board. The metal layer is formed between the optical waveguide and the back surface of the insulative layer of the electric circuit board. The metal layer is patterned to have a plurality of strips. Cores of the optical waveguide are disposed in a position corresponding to a site where the metal layer is removed by the patterning.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: July 1, 2014
    Assignee: Nitto Denko Corporation
    Inventors: Yuichi Tsujita, Yasuto Ishimura, Hiroyuki Hanazono, Naoyuki Tanaka, Yasufumi Yamamoto, Shotaro Masuda, Mayu Ozaki