Patents by Inventor Hiroyuki Hara

Hiroyuki Hara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140169721
    Abstract: A thrust race of a thrust roller bearing has a race portion and a cylindrical portion extending from the race portion in an axial direction. At a plurality of locations along a circumferential direction on the cylindrical portion, cutout portions are formed such that each of the cutout portions is recessed in the axial direction from a distal edge of the cylindrical portion toward the race portion. A protrusion is provided at a portion closer to the race portion from a bottom edge of each of the cutout portions such that the protrusion protrudes in a radial direction from the cylindrical portion toward a side away from the race portion. The protrusion serves as a race-retaining locking portion to prevent a race from moving out from a mating member on which the race is mounted.
    Type: Application
    Filed: February 20, 2014
    Publication date: June 19, 2014
    Applicant: NSK LTD.
    Inventors: Hiroyuki HARA, Kazuhiko KANOU, Tomoyuki YOKOTA
  • Patent number: 8736889
    Abstract: An image forming apparatus includes a processor, and a storage controller that writes band data to a storage device and reads the band data. The processor: (a) generates a write-side process and a read-side process; (b) generates a write-side thread by the write-side process; (c) generates a read-side thread and a file read thread by the read-side process; (d) notifies the read-side process of an identifier within the storage device, and causes the storage controller to sequentially write the band data; and (e) requests the file read thread to cause the storage controller to sequentially read out the band data corresponding to the identifier and causes the storage controller to sequentially read out the band data and one or more subsequent band data.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: May 27, 2014
    Assignee: KYOCERA Document Solutions Inc.
    Inventor: Hiroyuki Hara
  • Publication number: 20140063530
    Abstract: A CPU perform the steps of: (a) causing a compression/decompression processor to decompress the compressed data of one of three bands in the data area except for the first block in the band, and storing decompressed bitmap data in the data area; (b) rasterizing each of the intermediate data blocks in the band and synthesizing the rasterized data and the decompressed bitmap data in the band; and (c) causing the compression/decompression processor to compress the synthesized bitmap data and storing the compressed data in the data area. The CPU performs the steps (a) to (c) in different respective tasks in parallel, and performs the steps (a) to (c) along the order of (a), (b), (c) for each of the intermediate code blocks in each of the bands while using the 1st to the 3rd bitmap data area in turn for each of the steps (a) to (c).
    Type: Application
    Filed: November 10, 2013
    Publication date: March 6, 2014
    Applicant: KYOCERA DOCUMENT SOLUTIONS, INC.
    Inventor: Hiroyuki Hara
  • Publication number: 20140063554
    Abstract: A CPU perform the steps of: (a) causing a compression/decompression processor to decompress the compressed data of one of three bands in the data area except for the first block in the band, and storing decompressed bitmap data in the data area; (b) rasterizing each of the intermediate data blocks in the band and synthesizing the rasterized data and the decompressed bitmap data in the band; and (c) causing the compression/decompression processor to compress the synthesized bitmap data and storing the compressed data in the data area. The CPU performs the steps (a) to (c) in different respective tasks in parallel, and performs the steps (a) to (c) along the order of (a), (b), (c) for each of the intermediate code blocks in each of the bands while using the 1st to the 3rd bitmap data area in turn for each of the steps (a) to (c).
    Type: Application
    Filed: November 10, 2013
    Publication date: March 6, 2014
    Applicant: KYOCERA DOCUMENT SOLUTIONS, INC.
    Inventor: Hiroyuki Hara
  • Publication number: 20140063529
    Abstract: A CPU perform the steps of: (a) causing a compression/decompression processor to decompress the compressed data of one of three bands in the data area except for the first block in the band, and storing decompressed bitmap data in the data area; (b) rasterizing each of the intermediate data blocks in the band and synthesizing the rasterized data and the decompressed bitmap data in the band; and (c) causing the compression/decompression processor to compress the synthesized bitmap data and storing the compressed data in the data area. The CPU performs the steps (a) to (c) in different respective tasks in parallel, and performs the steps (a) to (c) along the order of (a), (b), (c) for each of the intermediate code blocks in each of the bands while using the 1st to the 3rd bitmap data area in turn for each of the steps (a) to (c).
    Type: Application
    Filed: November 10, 2013
    Publication date: March 6, 2014
    Applicant: KYOCERA DOCUMENT SOLUTIONS, INC.
    Inventor: Hiroyuki Hara
  • Patent number: 8661209
    Abstract: A data processing apparatus includes a storage controller and a processor. The storage controller is configured to write a series of data blocks constituting a particular unit of data to a storage and read out the series of data blocks from the storage. The processor is further configured to generate a write-side process and a read-side process, notify the read-side process from the write-side process of an identifier of a storage area in the storage, cause the storage controller to sequentially write the series of data blocks to the storage area using the write-side process, and cause the storage controller to read the series of data blocks from the storage area corresponding to the identifier using the read-side process after the identifier is received in the read-side process.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: February 25, 2014
    Assignee: KYOCERA Document Solutions Inc.
    Inventor: Hiroyuki Hara
  • Patent number: 8659528
    Abstract: An electro-optical device includes: a data line driver applying the signal potential in such a manner that a writing polarity is reversed more than once in the field time period, and the writing polarity of each of sub field time periods making up a certain field time period is the opposite of the writing polarity of the corresponding one of sub field time periods making up the next field time period; a scanning line driver applying the scanning signal in such a manner that a total length of the sub field time periods in which writing in one polarity is performed in each cycle of two consecutive fields one of which is an odd field and the other of which is an even field is different from a total length of the sub field time periods in which writing in the other polarity is performed in the each cycle of two consecutive fields.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: February 25, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Hiroyuki Hara
  • Patent number: 8643814
    Abstract: In at least one embodiment of the disclosure, a liquid crystal device comprises a plurality of conductive patterns formed of a conductive film in a peripheral region between an image display region and a sealing member. The conductive patterns are formed at a same layer as a plurality of pixel electrodes. An insulation film is formed on a side facing a counter substrate so as to correspond to the plurality of conductive patterns and a plurality of pixel electrodes. Peripheral electrodes are formed in a region overlapping the plurality of conductive patterns in a plan view on a side on which the counter substrate is located so as to correspond to the insulation film in the peripheral region.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: February 4, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Tomoki Yokota, Hiroyuki Hara
  • Patent number: 8619310
    Abstract: A CPU perform the steps of: (a) causing a compression/decompression processor to decompress the compressed data of one of three bands in the data area except for the first block in the band, and storing decompressed bitmap data in the data area; (b) rasterizing each of the intermediate data blocks in the band and synthesizing the rasterized data and the decompressed bitmap data in the band; and (c) causing the compression/decompression processor to compress the synthesized bitmap data and storing the compressed data in the data area. The CPU performs the steps (a) to (c) in different respective tasks in parallel, and performs the steps (a) to (c) along the order of (a), (b), (c) for each of the intermediate code blocks in each of the bands while using the 1st to the 3rd bitmap data area in turn for each of the steps (a) to (c).
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: December 31, 2013
    Assignee: Kyocera Document Solutions, Inc.
    Inventor: Hiroyuki Hara
  • Patent number: 8604725
    Abstract: According to one embodiment, a semiconductor device includes an electrostatic actuator including first and second lower electrodes, an upper electrode, and an insulating film provided between the upper electrode and the first and second lower electrodes, the first lower electrode and upper electrode configuring a first variable capacitance element, the second lower electrode and upper electrode configuring a second variable capacitance element, a first fixed capacitance element connected to the first lower electrode, a second fixed capacitance element connected to the second lower electrode, and a detection circuit connected to the upper electrode and configured to detect a charge amount stored in the insulating film.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: December 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tamio Ikehashi, Takayuki Miyazaki, Hiroyuki Hara
  • Patent number: 8598291
    Abstract: Antifouling composition containing a fluorocopolymer which contains from 30 to 70 mass % of polymerized units (a?) having a C1-6 perfluoroalkyl group, from 20 to 69 mass % of polymerized units (b?) having an alkylene oxide chain and from 1 to 10 mass % of polymerized units (c?) having an amino group, and which has anionic groups at its main chain terminals. Method of making.
    Type: Grant
    Filed: November 27, 2009
    Date of Patent: December 3, 2013
    Assignee: Asahi Glass Company, Limited
    Inventors: Hiroyuki Hara, Shuichiro Sugimoto, Takao Hirono, Takashige Maekawa
  • Publication number: 20130307585
    Abstract: A semiconductor integrated circuit comprises a state holding circuit that inputs an output of one inverter to another inverter with each other; an input circuit that causes a state of the state holding circuit to transition based on a data signal; a first first-conductive transistor that is inserted between an input of the one inverter and an output of the another inverter and is controlled by the data signal; and a first second-conductive transistor that is connected in parallel with the first first-conductive transistor and is controlled by the data signal.
    Type: Application
    Filed: July 23, 2013
    Publication date: November 21, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Chen kong Teh, Hiroyuki Hara
  • Patent number: 8557939
    Abstract: To provide an antifouling composition which is a fluorine-type antifouling composition using a short chain perfluoroalkyl group and which is excellent in antifouling properties and water/oil repellency and presents good durability against washing. An antifouling composition comprising a fluorocopolymer which comprises from 30 to 65 mass % of polymerized units (a) having a C1-6 perfluoroalkyl group, from 1 to 67 mass % of polymerized units (b1) having —(C2H4O)— and from 3 to 34 mass % of polymerized units (b2) having —(C4H8O)—, wherein the content of —(C2H4O)— is from 20 to 65 mass %, and the content of —(C4H8O)— is from 2 to 13 mass %.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: October 15, 2013
    Assignee: Asahi Glass Company, Limited
    Inventors: Hiroyuki Hara, Shuichiro Sugimoto, Takao Hirono, Takashige Maekawa
  • Patent number: 8519743
    Abstract: A semiconductor integrated circuit comprises a state holding circuit that inputs an output of one inverter to another inverter with each other; an input circuit that causes a state of the state holding circuit to transition based on a data signal; a first first-conductive transistor that is inserted between an input of the one inverter and an output of the another inverter and is controlled by the data signal; and a first second-conductive transistor that is connected in parallel with the first first-conductive transistor and is controlled by the data signal.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: August 27, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chen kong Teh, Hiroyuki Hara
  • Patent number: 8507580
    Abstract: To provide a process for efficiently producing a fluorine type antifouling composition employing a short chain Rf group, which can be made in the form of an aqueous dispersion containing substantially no volatile organic solvent and has a good soil release property (SR property). A process for producing an antifouling composition, which comprises a step of subjecting monomer components (Z) comprising from 30 to 80 mass % of a monomer (a) having a polyfluoroalkyl group in which the number of carbon atoms to which fluorine atoms are bonded is from 4 to 6, and from 20 to 70 mass % of a monomer (b) having no polyfluoroalkyl group and having a hydrophilic group, to solution polymerization in a volatile organic solvent having a boiling point of at most 100° C.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: August 13, 2013
    Assignee: Asahi Glass Company, Limited
    Inventors: Hiroyuki Hara, Shuichiro Sugimoto, Takao Hirono
  • Publication number: 20130106318
    Abstract: According to one embodiment, a semiconductor device includes an electrostatic actuator including first and second lower electrodes, an upper electrode, and an insulating film provided between the upper electrode and the first and second lower electrodes, the first lower electrode and upper electrode configuring a first variable capacitance element, the second lower electrode and upper electrode configuring a second variable capacitance element, a first fixed capacitance element connected to the first lower electrode, a second fixed capacitance element connected to the second lower electrode, and a detection circuit connected to the upper electrode and configured to detect a charge amount stored in the insulating film.
    Type: Application
    Filed: December 19, 2012
    Publication date: May 2, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tamio Ikehashi, Takayuki Miyazaki, Hiroyuki Hara
  • Patent number: 8415982
    Abstract: A semiconductor integrated circuit device includes: a first inverter constituted by a first transistor configured to charge a charge point based on an input signal, and a second transistor configured to discharge a discharge point based on the input signal; a P-type third transistor and an N-type fourth transistor with drain-source paths provided in parallel between the charge point and the discharge point; and a second inverter configured to invert a potential of the charge point or the discharge point and supply the inverted potential to gates of the third and fourth transistors, and obtain a delay signal of the input signal from the charge point or the discharge point. The semiconductor integrated circuit device secures a sufficient delay time with a small area.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: April 9, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chenkong Teh, Hiroyuki Hara
  • Publication number: 20130021657
    Abstract: An electrooptic device includes first and second substrates that are disposed opposing each other with an electrooptic material layer therebetween, a sealing material that bonds the first and second substrates, a pixel area, and an ion trap portion between the pixel area and the sealing material. The ion trap portion includes first and second electrodes that are formed in a comb-tooth shape and are disposed so that branch electrodes of the first electrode and branch electrodes of the second electrode are engaged with each other. A direction of the branch electrodes intersects with an orientation direction of the electrooptic material at an interface between the electrooptic material layer and the first substrate.
    Type: Application
    Filed: July 17, 2012
    Publication date: January 24, 2013
    Applicant: Seiko Epson Corporation
    Inventors: Naoki Tomikawa, Hiroyuki Hara, Tomoki Yokota
  • Publication number: 20120250093
    Abstract: An image forming apparatus includes a processor, and a storage controller that writes band data to a storage device and reads the band data. The processor: (a) generates a write-side process and a read-side process; (b) generates a write-side thread by the write-side process; (c) generates a read-side thread and a file read thread by the read-side process; (d) notifies the read-side process of an identifier within the storage device, and causes the storage controller to sequentially write the band data; and (e) requests the file read thread to cause the storage controller to sequentially read out the band data corresponding to the identifier and causes the storage controller to sequentially read out the band data and one or more subsequent band data.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 4, 2012
    Applicant: KYOCERA MITA CORPORATION
    Inventor: Hiroyuki Hara
  • Publication number: 20120249919
    Abstract: In at least one embodiment of the disclosure, a liquid crystal device comprises a plurality of conductive patterns formed of a conductive film in a peripheral region between an image display region and a sealing member. The conductive patterns are formed at a same layer as a plurality of pixel electrodes. An insulation film is formed on a side facing a counter substrate so as to correspond to the plurality of conductive patterns and a plurality of pixel electrodes. Peripheral electrodes are formed in a region overlapping the plurality of conductive patterns in a plan view on a side on which the counter substrate is located so as to correspond to the insulation film in the peripheral region.
    Type: Application
    Filed: March 26, 2012
    Publication date: October 4, 2012
    Applicant: Seiko Epson Corporation
    Inventors: Tomoki Yokota, Hiroyuki Hara