Patents by Inventor Hiroyuki Kawashima

Hiroyuki Kawashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240127830
    Abstract: This encoding device comprises: a downmix circuit that switches mixing processing according to the characteristic of an input stereo signal to generate either a first stereo signal or a second stereo signal obtained by mixing processing of a left channel signal and a right channel signal; a first encoding circuit that encodes the first stereo signal; and a second encoding circuit that encodes two signals included in the second stereo signal. The second encoding circuit performs monaural encoding on the basis of the encoding mode of the first encoding circuit in a first section in which switching from the first stereo signal to the second stereo signal is performed and/or a second section in which switching from the second stereo signal to the first stereo signal is performed.
    Type: Application
    Filed: October 15, 2021
    Publication date: April 18, 2024
    Applicant: Panasonic Intellectual Property Corporation of America
    Inventors: Yuichi KAMIYA, Takuya KAWASHIMA, Akira HARADA, Hiroyuki EHARA
  • Patent number: 11958182
    Abstract: A mobile body system for managing a mobile body that moves within a predetermined area includes a mobile body associated with a guest group including one or more guests, and a managing apparatus configured to manage an outer appearance of the mobile body. The managing apparatus includes an activity collector configured to collect activity information indicative of an activity of the guest within the predetermined area, and an outer appearance manager configured to change the outer appearance of the mobile body viewed by the guest based on the activity information collected by the activity collector.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: April 16, 2024
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Mutsumi Kawashima, Tomoaki Miyazawa, Masato Noritake, Nobuhiro Nishikawa, Masato Kurima, Tokuyuki Nishikawa, Reiko Tomita, Takaaki Kato, Hiroyuki Tomita, Daisaku Kato
  • Publication number: 20240122065
    Abstract: The present invention provides: a metal patterning material which exhibits excellent heat resistance and is suppressed in the formation of a metal thin film on a film surface; an amine compound; a method for forming a metal pattern using these; and an electronic device.
    Type: Application
    Filed: August 11, 2021
    Publication date: April 11, 2024
    Applicant: TOSOH CORPORATION
    Inventors: Naoki MATSUMOTO, Hiroyuki KAWASHIMA, Shintaro NOMURA
  • Publication number: 20240101483
    Abstract: To provide at least one of: a powder composition from which a calcined body with similar processability can be produced without requiring the application of different forming conditions and calcination conditions for each composition; a method for producing the powder composition; a calcined body produced from the powder composition; a method for producing the calcined body; and uses thereof. A powder composition including: two or more types of zirconia in which a lanthanoid rare-earth element is dissolved; a transition metal element other than zirconium and hafnium; and a remainder composed of zirconia stabilized only by one or more selected from the group consisting of yttrium, calcium and magnesium, wherein a different lanthanoid rare-earth element is dissolved in each zirconia in which the lanthanoid rare-earth element is dissolved, and a transition metal element content is 1500 ppm or less.
    Type: Application
    Filed: January 19, 2022
    Publication date: March 28, 2024
    Applicant: TOSOH CORPORATION
    Inventors: Sho AZECHI, Yuki USHIO, Takahiro SHIMIZU, Yuya HIGUCHI, Hitoshi NAGAYAMA, Hiroyuki FUJISAKI, Kenji IMAI, Risa KAWASHIMA
  • Publication number: 20230361047
    Abstract: A semiconductor device according to an embodiment of the present disclosure includes: a first substrate including a first junction portion; and a second substrate including a second junction portion. The second junction portion is joined to the first junction portion. The first substrate further includes a first multilayer wiring layer in which one surface of a first wiring line faces a first insulating layer and another surface opposed to the one surface is in contact with a second insulating layer. The first multilayer wiring layer is electrically coupled to the first junction portion via the first insulating layer. The first wiring line is formed closest to a junction surface with the second substrate. The second insulating layer has a lower relative dielectric constant than a relative dielectric constant of the first insulating layer.
    Type: Application
    Filed: July 13, 2023
    Publication date: November 9, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroyuki KAWASHIMA, Ryoichi NAKAMURA, Yoshihisa KAGAWA, Yuusaku KOBAYASHI
  • Patent number: 11810851
    Abstract: The present technology relates to a semiconductor device in which a MIM capacitive element can be formed without any process damage, and a method for manufacturing the semiconductor device. In a semiconductor device, wiring layers of a first multilayer wiring layer formed on a first semiconductor substrate and a second multilayer wiring layer formed on a second semiconductor substrate are bonded to each other by wafer bonding. The semiconductor device includes a capacitive element including an upper electrode, a lower electrode, and a capacitive insulating film between the upper electrode and the lower electrode. One electrode of the upper electrode and the lower electrode is formed with a first conductive layer of the first multilayer wiring layer and a second conductive layer of the second multilayer wiring layer. The present technology can be applied to a semiconductor device or the like formed by joining two semiconductor substrates, for example.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: November 7, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hitoshi Okano, Hiroyuki Kawashima
  • Patent number: 11749609
    Abstract: A semiconductor device according to an embodiment of the present disclosure includes: a first substrate including a first junction portion; and a second substrate including a second junction portion. The second junction portion is joined to the first junction portion. The first substrate further includes a first multilayer wiring layer in which one surface of a first wiring line faces a first insulating layer and another surface opposed to the one surface is in contact with a second insulating layer. The first multilayer wiring layer is electrically coupled to the first junction portion via the first insulating layer. The first wiring line is formed closest to a junction surface with the second substrate. The second insulating layer has a lower relative dielectric constant than a relative dielectric constant of the first insulating layer.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: September 5, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroyuki Kawashima, Ryoichi Nakamura, Yoshihisa Kagawa, Yuusaku Kobayashi
  • Patent number: 11621283
    Abstract: To provide a semiconductor device, an image pickup device, and a method for manufacturing the semiconductor device that reduce wiring capacity by using gaps and maintain mechanical strength and reliability. A semiconductor device including: a multilayered wiring layer in which insulating layers and diffusion preventing layers are alternately laminated and a wiring layer is provided inside; a through-hole that is provided to penetrate through at least one or more insulating layers from one surface of the multilayered wiring layer and has an inside covered with a protective side wall; and a gap that is provided in at least one or more insulating layers immediately below the through-hole.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: April 4, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Hiroyuki Kawashima
  • Publication number: 20220302020
    Abstract: The present technology relates to a semiconductor device in which a MIM capacitive element can be formed without any process damage, and a method for manufacturing the semiconductor device. In a semiconductor device, wiring layers of a first multilayer wiring layer formed on a first semiconductor substrate and a second multilayer wiring layer formed on a second semiconductor substrate are bonded to each other by wafer bonding. The semiconductor device includes a capacitive element including an upper electrode, a lower electrode, and a capacitive insulating film between the upper electrode and the lower electrode. One electrode of the upper electrode and the lower electrode is formed with a first conductive layer of the first multilayer wiring layer and a second conductive layer of the second multilayer wiring layer. The present technology can be applied to a semiconductor device or the like formed by joining two semiconductor substrates, for example.
    Type: Application
    Filed: February 28, 2022
    Publication date: September 22, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hitoshi OKANO, Hiroyuki KAWASHIMA
  • Patent number: 11296020
    Abstract: The present technology relates to a semiconductor device in which a MIM capacitive element can be formed without any process damage, and a method for manufacturing the semiconductor device. In a semiconductor device, wiring layers of a first multilayer wiring layer formed on a first semiconductor substrate and a second multilayer wiring layer formed on a second semiconductor substrate are bonded to each other by wafer bonding. The semiconductor device includes a capacitive element including an upper electrode, a lower electrode, and a capacitive insulating film between the upper electrode and the lower electrode. One electrode of the upper electrode and the lower electrode is formed with a first conductive layer of the first multilayer wiring layer and a second conductive layer of the second multilayer wiring layer. The present technology can be applied to a semiconductor device or the like formed by joining two semiconductor substrates, for example.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: April 5, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Hitoshi Okano, Hiroyuki Kawashima
  • Patent number: 11271027
    Abstract: To reduce the capacitance between wiring lines of a semiconductor device, while maintaining mechanical strength and reliability. A semiconductor device including: a multilayer wiring layer in which a plurality of interlayer films and a plurality of diffusion preventing films are alternately stacked, and a wiring line is formed in the interlayer films; a contact via that penetrates a via insulating layer formed on one surface of the multilayer wiring layer, and is electrically connected to the wiring line of the multilayer wiring layer; a through hole that penetrates at least one of the interlayer films and the diffusion preventing films from the other surface of the multilayer wiring layer on the opposite side from the one surface; and an air gap that is connected to the through hole, and is formed in at least one of the interlayer films, to expose the contact via.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: March 8, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Hiroyuki Kawashima
  • Patent number: 11180865
    Abstract: It is an object to provide a method for producing a diamond substrate effective for reducing various defects including dislocation defects and a foundation substrate used for the same. This object is achieved by a foundation substrate for forming a diamond film by a chemical vapor deposition method, wherein an off angle is provided to the surface of the foundation substrate with respect to a predetermined crystal plane orientation.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: November 23, 2021
    Assignees: SHIN-ETSU CHEMICAL CO., LTD., NATIONAL INSTITUTE OF ADVANCED, INDUSTRIAL SCIENCE AND TECHNOLOGY, NATIONAL UNIVERSITY CORPORATION, KANAZAWA UNIVERSITY
    Inventors: Hitoshi Noguchi, Toshiharu Makino, Masahiko Ogura, Hiromitsu Kato, Hiroyuki Kawashima, Satoshi Yamasaki, Norio Tokuda
  • Patent number: 11066757
    Abstract: A method for manufacturing a diamond substrate, including: a first step of preparing patterned diamond on a foundation surface, a second step of growing diamond from the patterned diamond prepared in the first step to form the diamond in a pattern gap of the patterned diamond prepared in the first step, a third step of removing the patterned diamond prepared in the first step to form a patterned diamond composed of the diamond formed in the second step, and a fourth step of growing diamond from the patterned diamond formed in the third step to form the diamond in a pattern gap of the patterned diamond formed in the third step. There can be provided a method for manufacturing a diamond substrate which can sufficiently suppress dislocation defects, a high-quality diamond substrate, and a freestanding diamond substrate.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: July 20, 2021
    Assignees: Shin-Etsu Chemical Co., Ltd., National Institute of Advanced Industrial Science and Technology, National University Corporation Kanazawa University
    Inventors: Hitoshi Noguchi, Shozo Shirai, Toshiharu Makino, Masahiko Ogura, Hiromitsu Kato, Hiroyuki Kawashima, Daisuke Kuwabara, Satoshi Yamasaki, Daisuke Takeuchi, Norio Tokuda, Takao Inokuma, Tsubasa Matsumoto
  • Publication number: 20210183778
    Abstract: A semiconductor device according to an embodiment of the present disclosure includes: a first substrate including a first junction portion; and a second substrate including a second junction portion. The second junction portion is joined to the first junction portion. The first substrate further includes a first multilayer wiring layer in which one surface of a first wiring line faces a first insulating layer and another surface opposed to the one surface is in contact with a second insulating layer. The first multilayer wiring layer is electrically coupled to the first junction portion via the first insulating layer. The first wiring line is formed closest to a junction surface with the second substrate. The second insulating layer has a lower relative dielectric constant than a relative dielectric constant of the first insulating layer.
    Type: Application
    Filed: June 11, 2019
    Publication date: June 17, 2021
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroyuki KAWASHIMA, Ryoichi NAKAMURA, Yoshihisa KAGAWA, Yuusaku KOBAYASHI
  • Publication number: 20210118922
    Abstract: To provide a semiconductor device, an image pickup device, and a method for manufacturing the semiconductor device that reduce wiring capacity by using gaps and maintain mechanical strength and reliability. A semiconductor device including: a multilayered wiring layer in which insulating layers and diffusion preventing layers are alternately laminated and a wiring layer is provided inside; a through-hole that is provided to penetrate through at least one or more insulating layers from one surface of the multilayered wiring layer and has an inside covered with a protective side wall; and a gap that is provided in at least one or more insulating layers immediately below the through-hole.
    Type: Application
    Filed: December 30, 2020
    Publication date: April 22, 2021
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Hiroyuki KAWASHIMA
  • Publication number: 20210090987
    Abstract: The present technology relates to a semiconductor device in which a MIM capacitive element can be formed without any process damage, and a method for manufacturing the semiconductor device. In a semiconductor device, wiring layers of a first multilayer wiring layer formed on a first semiconductor substrate and a second multilayer wiring layer formed on a second semiconductor substrate are bonded to each other by wafer bonding. The semiconductor device includes a capacitive element including an upper electrode, a lower electrode, and a capacitive insulating film between the upper electrode and the lower electrode. One electrode of the upper electrode and the lower electrode is formed with a first conductive layer of the first multilayer wiring layer and a second conductive layer of the second multilayer wiring layer. The present technology can be applied to a semiconductor device or the like formed by joining two semiconductor substrates, for example.
    Type: Application
    Filed: December 7, 2018
    Publication date: March 25, 2021
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hitoshi OKANO, Hiroyuki KAWASHIMA
  • Publication number: 20210066380
    Abstract: To reduce the capacitance between wiring lines of a semiconductor device, while maintaining mechanical strength and reliability. A semiconductor device including: a multilayer wiring layer in which a plurality of interlayer films and a plurality of diffusion preventing films are alternately stacked, and a wiring line is formed in the interlayer films; a contact via that penetrates a via insulating layer formed on one surface of the multilayer wiring layer, and is electrically connected to the wiring line of the multilayer wiring layer; a through hole that penetrates at least one of the interlayer films and the diffusion preventing films from the other surface of the multilayer wiring layer on the opposite side from the one surface; and an air gap that is connected to the through hole, and is formed in at least one of the interlayer films, to expose the contact via.
    Type: Application
    Filed: November 30, 2018
    Publication date: March 4, 2021
    Inventor: HIROYUKI KAWASHIMA
  • Patent number: 10910416
    Abstract: To provide a semiconductor device, an image pickup device, and a method for manufacturing the semiconductor device that reduce wiring capacity by using gaps and maintain mechanical strength and reliability. A semiconductor device including: a multilayered wiring layer in which insulating layers and diffusion preventing layers are alternately laminated and a wiring layer is provided inside; a through-hole that is provided to penetrate through at least one or more insulating layers from one surface of the multilayered wiring layer and has an inside covered with a protective side wall; and a gap that is provided in at least one or more insulating layers immediately below the through-hole.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: February 2, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Hiroyuki Kawashima
  • Patent number: 10460604
    Abstract: A collision determination apparatus used in a mobile body includes: a receiver receiving radio waves from reference stations; a pseudo range identifying unit identifying a pseudo range to a captured reference station; a self-single difference calculation unit calculating a self-single difference between a first reference station and a second reference station; a transmission unit transmitting a pseudo range associated information into surrounding the mobile body; a reception unit receiving the pseudo range associated information of an external apparatus; an external single difference identifying unit identifying an external single difference between the pseudo ranges to the first and second reference stations; a double difference calculating unit calculating a double difference between the self-single difference and the external single difference; and an approaching relationship determination unit determining whether or not the double difference tends to decrease and determining an approaching relationship wh
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: October 29, 2019
    Assignee: DENSO CORPORATION
    Inventors: Yasunobu Sugiura, Hiroyuki Kawashima
  • Publication number: 20190181168
    Abstract: To provide a semiconductor device, an image pickup device, and a method for manufacturing the semiconductor device that reduce wiring capacity by using gaps and maintain mechanical strength and reliability. A semiconductor device including: a multilayered wiring layer in which insulating layers and diffusion preventing layers are alternately laminated and a wiring layer is provided inside; a through-hole that is provided to penetrate through at least one or more insulating layers from one surface of the multilayered wiring layer and has an inside covered with a protective side wall; and a gap that is provided in at least one or more insulating layers immediately below the through-hole.
    Type: Application
    Filed: June 7, 2017
    Publication date: June 13, 2019
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Hiroyuki KAWASHIMA