Patents by Inventor Hiroyuki Nakamoto

Hiroyuki Nakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130013966
    Abstract: An electronic apparatus includes an error detection times acquiring module and a waiting module. The error detection times acquiring module acquires the number of reading error detection times of a program according to a power-ON instruction instructing a power-ON operation, the number of error detection times being stored in a storage module. The waiting module waits for a reception of data capable of recognizing a communication counterpart device when the number of error detection times is more than a predetermined value by comparing the acquired number of error detection times with the predetermined value.
    Type: Application
    Filed: April 18, 2012
    Publication date: January 10, 2013
    Inventor: Hiroyuki Nakamoto
  • Patent number: 8289197
    Abstract: A system has a corrected unit, and a correction unit that performs binary search of a correction value with which an output of the corrected unit gets close to a reference value and feeds back the correction value to the corrected unit. The correction unit performs the additional comparison for comparing a first output of the corrected unit corresponding to a first correction value searched by the binary search and a second output, which is an output of the corrected unit corresponding to a second correction value that is adjacent to the first correction value and is an output that the voltage relationship to the reference value is opposite to the first output, and for selecting the first or second correction value corresponding to the first or second output closer to the reference value, and feeds back the selected correction value to the corrected unit.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: October 16, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hiroyuki Nakamoto
  • Publication number: 20120235733
    Abstract: A detector circuit, has a first diode, to an anode of which an AC signal is input and to which a constant voltage is supplied, a second diode, to an anode of which the constant voltage is supplied, and a difference current generation circuit, which generates the difference current between a first current flowing in the first diode and a second current flowing in the second diode.
    Type: Application
    Filed: February 27, 2012
    Publication date: September 20, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Hiroyuki NAKAMOTO
  • Publication number: 20120217822
    Abstract: A variable capacitance circuit includes: a prescribed node, to which an alternate current signal with a reference potential as a center voltage is applied; a first capacitor connected to the prescribed node; a second capacitor connected between the first capacitor and the reference potential; a third capacitor and a transistor for controlling capacitance, provide between a first node between the second capacitor and the first capacitor, and the reference potential; and a bias circuit which applies a first bias voltage to a second node between the third capacitor and the transistor.
    Type: Application
    Filed: November 29, 2011
    Publication date: August 30, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Hiroyuki NAKAMOTO
  • Publication number: 20120126907
    Abstract: An oscillation circuit has a first inverter connected to an external piezoelectric resonator, a first feedback resistor disposed between input/output terminals of the first inverter, first/second variable capacitive elements connected to input/output of the first inverter, a charging circuit supplying input/output terminal with a reference current to charge the capacitive element, a comparator comparing a charging voltage of input/output with a reference voltage, and a control circuit that, in a calibration operation, at a first time, causes the charging circuit to start supply the reference current to the input terminal or the output terminal, and, at a second time after the first time, generates the control signal for setting a capacitance value of the first or second variable capacitive element so that the charging voltage becomes close to the reference voltage according to a comparison result of the comparator.
    Type: Application
    Filed: August 24, 2011
    Publication date: May 24, 2012
    Applicants: FUJITSU SEMICONDUCTOR LIMITED, FUJITSU LIMITED
    Inventors: Hiroyuki NAKAMOTO, Hiroyuki Ito
  • Patent number: 8164632
    Abstract: A picture is scrolled on a display 5 to be measured, and the scrolling moving picture is pursuit-captured by a color camera 3 so as to obtain a pursuit-captured moving picture image. A moving picture response curve using received light intensity data obtained based upon the pursuit-captured moving picture image is converted into a color moving picture response curve using emission intensity of display elements of the display 5 to be measured. The coloration of an edge part of the pursuit-captured moving picture image is decomposed into the respective color components, by which objective quantitative evaluations of color shifting can be made.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: April 24, 2012
    Assignee: Otsuka Electronics Co., Ltd.
    Inventors: Yoshi Enami, Yoshihisa Furukawa, Hiroyuki Nakamoto, Tsutomu Mizuguchi
  • Patent number: 8049651
    Abstract: A ?? modulation circuit that includes a first integrator and second integrator coupled in series, a quantizer coupled to an output of the second integrator, a delay device disposed in a feedback path from an output of the quantizer to an input of the first and second integrators, an adder which generates a difference between an output and an input of the quantizer, and a feedback circuit including a delay device which couples an output of the adder to an output of one of the first and second integrators.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: November 1, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hiroyuki Nakamoto
  • Patent number: 8014747
    Abstract: An amplitude detecting device of the present art increases the slope of the change in output voltage corresponding to the change in amplitude of an input signal to improve the detection accuracy of amplitude change of input signal, without changing the dynamic range of the device. An amplitude detecting device of the art includes a plurality of amplifiers that amplify an input signal according to a predefined amplification rate, an amplitude detector that detects the amplitude of the signal amplified by the amplifiers, an operation circuit that operates the signal detected by the amplitude detector and obtains the amplitude value of the input signal, and a switch circuit that sets whether the signal detected by the amplitude detector is to be transmitted to the operation circuit or not.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: September 6, 2011
    Assignee: Fujitsu Limited
    Inventor: Hiroyuki Nakamoto
  • Publication number: 20110128045
    Abstract: A system has a corrected unit, and a correction unit that performs binary search of a correction value with which an output of the corrected unit gets close to a reference value and feeds back the correction value to the corrected unit. The correction unit performs the additional comparison for comparing a first output of the corrected unit corresponding to a first correction value searched by the binary search and a second output, which is an output of the corrected unit corresponding to a second correction value that is adjacent to the first correction value and is an output that the voltage relationship to the reference value is opposite to the first output, and for selecting the first or second correction value corresponding to the first or second output closer to the reference value, and feeds back the selected correction value to the corrected unit.
    Type: Application
    Filed: November 15, 2010
    Publication date: June 2, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Hiroyuki Nakamoto
  • Publication number: 20100214143
    Abstract: A ?? modulation circuit that includes a first integrator and second integrator coupled in series, a quantizer coupled to an output of the second integrator, a delay device disposed in a feedback path from an output of the quantizer to an input of the first and second integrators, an adder which generates a difference between an output and an input of the quantizer, and a feedback circuit including a delay device which couples an output of the adder to an output of one of the first and second integrators.
    Type: Application
    Filed: January 13, 2010
    Publication date: August 26, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Hiroyuki NAKAMOTO
  • Patent number: 7456774
    Abstract: An encoder circuit and A/D converter that can minimize the error of an encoder output with respect to all the possible combinations of thermometer codes are desired to be provided. To this end, an encoder circuit has a logic thereof configured to take a thermometer code as an input and to output as an encoded value a center value of a range in which one or more encoded values are distributed, the one or more encoded values corresponding to positions of one or more boundaries between “0” and “1” appearing in the thermometer code.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: November 25, 2008
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Nakamoto, Kunihiko Gotoh
  • Publication number: 20080191889
    Abstract: An amplitude detecting device of the present art increases the slope of the change in output voltage corresponding to the change in amplitude of an input signal to improve the detection accuracy of amplitude change of input signal, without changing the dynamic range of the device. An amplitude detecting device of the art includes a plurality of amplifiers that amplify an input signal according to a predefined amplification rate, an amplitude detector that detects the amplitude of the signal amplified by the amplifiers, an operation circuit that operates the signal detected by the amplitude detector and obtains the amplitude value of the input signal, and a switch circuit that sets whether the signal detected by the amplitude detector is to be transmitted to the operation circuit or not.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 14, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Hiroyuki NAKAMOTO
  • Publication number: 20070285301
    Abstract: An encoder circuit and A/D converter that can minimize the error of an encoder output with respect to all the possible combinations of thermometer codes are desired to be provided. To this end, an encoder circuit has a logic thereof configured to take a thermometer code as an input and to output as an encoded value a center value of a range in which one or more encoded values are distributed, the one or more encoded values corresponding to positions of one or more boundaries between “0” and “1” appearing in the thermometer code.
    Type: Application
    Filed: August 16, 2007
    Publication date: December 13, 2007
    Inventors: Hiroyuki Nakamoto, Kunihiko Gotoh
  • Patent number: 7271757
    Abstract: An encoder circuit and A/D converter that can minimize the error of an encoder output with respect to all the possible combinations of thermometer codes are desired to be provided. To this end, an encoder circuit has a logic thereof configured to take a thermometer code as an input and to output as an encoded value a center value of a range in which one or more encoded values are distributed, the one or more encoded values corresponding to positions of one or more boundaries between “0” and “1” appearing in the thermometer code.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: September 18, 2007
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Nakamoto, Kunihiko Gotoh
  • Publication number: 20070211146
    Abstract: A picture is scrolled on a display 5 to be measured, and the scrolling moving picture is pursuit-captured by a color camera 3 so as to obtain a pursuit-captured moving picture image. A moving picture response curve using received light intensity data obtained based upon the pursuit-captured moving picture image is converted into a color moving picture response curve using emission intensity of display elements of the display 5 to be measured. The coloration of an edge part of the pursuit-captured moving picture image is decomposed into the respective color components, by which objective quantitative evaluations of color shifting can be made.
    Type: Application
    Filed: February 27, 2007
    Publication date: September 13, 2007
    Inventors: Yoshi Enami, Yoshihisa Furukawa, Hiroyuki Nakamoto, Tsutomu Mizuguchi
  • Patent number: 7068548
    Abstract: A semiconductor integrated circuit includes a substrate, a digital circuit formed on a triple well formed in the substrate, a first node configured to supply a well potential of the digital circuit, a second node separate from the first node, and a substrate-potential supplying circuit, formed on the substrate, having an input node to receive an input potential from the second node and an output node to supply a substrate potential to the substrate, the substrate-potential supplying circuit having no direct-current path into which a direct current substantially flows through the input node, and configured to generate at the output node an output potential following the input potential.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: June 27, 2006
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Nakamoto, Kunihiko Gotoh
  • Publication number: 20050249005
    Abstract: A semiconductor integrated circuit includes a substrate, a digital circuit formed on a triple well formed in the substrate, a first node configured to supply a well potential of the digital circuit, a second node separate from the first node, and a substrate-potential supplying circuit, formed on the substrate, having an input node to receive an input potential from the second node and an output node to supply a substrate potential to the substrate, the substrate-potential supplying circuit having no direct-current path into which a direct current substantially flows through the input node, and configured to generate at the output node an output potential following the input potential.
    Type: Application
    Filed: December 16, 2004
    Publication date: November 10, 2005
    Inventors: Hiroyuki Nakamoto, Kunihiko Gotoh
  • Publication number: 20050134495
    Abstract: An encoder circuit and A/D converter that can minimize the error of an encoder output with respect to all the possible combinations of thermometer codes are desired to be provided. To this end, an encoder circuit has a logic thereof configured to take a thermometer code as an input and to output as an encoded value a center value of a range in which one or more encoded values are distributed, the one or more encoded values corresponding to positions of one or more boundaries between “0” and “1” appearing in the thermometer code.
    Type: Application
    Filed: February 15, 2005
    Publication date: June 23, 2005
    Inventors: Hiroyuki Nakamoto, Kunihiko Gotoh
  • Patent number: 6822599
    Abstract: The integrated circuit comprises an interior division circuit to hold a first amount of charge corresponding to a weighted sum of a first analog voltage and a second analog voltage corresponding to a digital signal, an exterior division circuit to hold a second amount of charge corresponding to a difference between the first analog voltage and second analog voltage, and an amplifying circuit to generate a voltage not within the range between the first analog voltage and the second analog voltage by amplifying the voltage depending on the sum of the first amount of charge and the second amount of charge. The integrated circuit may provide a lower consumption and small area integrated circuit which can generate an exterior division voltage of higher accuracy.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: November 23, 2004
    Assignee: Fujitsu Limited
    Inventors: Masato Yoshioka, Kunihiko Gotoh, Hiroshi Yamazaki, Masahiro Kudo, Hiroyuki Nakamoto
  • Publication number: 20040113830
    Abstract: The integrated circuit comprises an interior division circuit to hold a first amount of charge corresponding to a weighted sum of a first analog voltage and a second analog voltage corresponding to a digital signal, an exterior division circuit to hold a second amount of charge corresponding to a difference between the first analog voltage and second analog voltage, and an amplifying circuit to generate a voltage not within the range between the first analog voltage and the second analog voltage by amplifying the voltage depending on the sum of the first amount of charge and the second amount of charge. The integrated circuit may provide a lower consumption and small area integrated circuit which can generate an exterior division voltage of higher accuracy.
    Type: Application
    Filed: December 10, 2003
    Publication date: June 17, 2004
    Inventors: Masato Yoshioka, Kunihiko Gotoh, Hiroshi Yamazaki, Masahiro Kudo, Hiroyuki Nakamoto