Patents by Inventor Hiroyuki Nakamura

Hiroyuki Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230112677
    Abstract: A film bulk acoustic wave resonator (FBAR) is disclosed with raised and recessed frame portions formed in a top electrode. The FBAR can include a substrate, a piezoelectric film supported to oscillate in a direction opposite to a main surface of the substrate, and a pair of top and bottom electrodes formed respectively on top and bottom surfaces of the film. The recessed frame portion and the raised frame portion can be formed to extend adjacent to each other along a periphery of an active region of the film oscillating during an operation of the film on a top surface of the top electrode.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 13, 2023
    Inventors: Gong Bin Tang, Ousmane I Barry, Hiroyuki Nakamura
  • Publication number: 20230112443
    Abstract: A piezoelectric microelectromechanical systems device can include a cavity bounded by walls and an asymmetrical bimorph structure at least partially spanning the cavity that includes at least a piezoelectric layer and two electrode layers. The electrode layers can have relative thicknesses configured to compensate for expected temperature stress in the bimorph structure. Thus, metals having different thicknesses can be positioned and configured to compensate deflection due to thermal stress of any or all of the piezoelectric layer, the first metal layer, and second metal layer and a substrate. A method for making the piezoelectric microelectromechanical systems device is also provided.
    Type: Application
    Filed: September 28, 2022
    Publication date: April 13, 2023
    Inventors: Siarhei Dmitrievich Barsukou, Myeong Gweon Gu, Hiroyuki Nakamura
  • Patent number: 11626353
    Abstract: According to the present disclosure, a method of manufacturing a semiconductor device includes the steps of (a) preparing a lead frame including a switching element die pad, a control element die pad, and a third-side side rail portion, (b) mounting a switching element and a diode element on the switching element die pad and mounting a control element configured to control the switching element on the control element die pad, (c) sealing the switching element, the diode element, and the control element with a mold resin such that the power side terminal, the control side terminal, and a part of the third-side side rail portion protrude outward, and (d) forming a third-side side rail terminal by cutting the third-side side rail portion, the third-side side rail terminal extending from a part of the third-side side rail portion.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: April 11, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shuhei Yokoyama, Hiroyuki Nakamura
  • Publication number: 20230105794
    Abstract: A Lamb wave filter is provided which has improved out of band rejection, the filter including a substrate having a center region and two edge regions, a first set of electrodes arranged as a first interdigital transducer displaced on one of the two edge regions and configured to receive an input signal, a second set of electrodes arranged as a second interdigital transducer displaced on the other of the two edge regions and configured to provide a filtered output signal, and a third set of electrodes disposed parallel to the first and second sets of electrodes on the center region of the substrate.
    Type: Application
    Filed: October 4, 2022
    Publication date: April 6, 2023
    Inventors: Siarhei Dmitrievich Barsukou, Hiroyuki Nakamura
  • Publication number: 20230106654
    Abstract: A semiconductor device includes a semiconductor substrate in which a first region having a freewheeling diode arranged therein, second regions having an IGBT arranged therein, and a withstand-voltage retention region surrounding the first region and the second regions in plan view are defined. The semiconductor substrate has a first main surface and a second main surface. The semiconductor substrate includes an anode layer having a first conductivity type, which is arranged in the first main surface of the first region, and a diffusion layer having the first conductivity type, which is arranged in the first main surface of the withstand-voltage retention region adjacently to the anode layer. A first trench is arranged in the first main surface on a side of the anode layer with respect to a boundary between the anode layer and the diffusion layer.
    Type: Application
    Filed: December 6, 2022
    Publication date: April 6, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hiroyuki NAKAMURA, Shinya SONEDA
  • Publication number: 20230104257
    Abstract: A piezoelectric microelectromechanical system microphone comprises a support substrate, a membrane including a piezoelectric material attached to the support substrate and configured to deform and generate an electrical potential responsive to impingement of sound waves on the membrane, and a compliant anchor including a trench defined in the support substrate about a portion of a perimeter of the membrane to increase sensitivity of the piezoelectric microelectromechanical system microphone.
    Type: Application
    Filed: October 4, 2022
    Publication date: April 6, 2023
    Inventors: Siarhei Dmitrievich Barsukou, Hiroyuki Nakamura, Keiichi Maki, Takanori Yasuda, Ousmane I Barry
  • Publication number: 20230105726
    Abstract: A film bulk acoustic wave resonator (FBAR) is disclosed with recessed and raised frame portions in the piezoelectric film. The FBAR can include a substrate, the piezoelectric film supported to oscillate in a direction opposite to a main surface of the substrate, and a pair of top and bottom electrodes formed respectively on top and bottom surfaces of the film. The recessed frame portion and the raised frame portion can be formed in the film to extend adjacent to each other along a periphery of an active region of the film oscillating during an operation of the film on a top surface of the top electrode.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 6, 2023
    Inventors: Gong Bin Tang, Ousmane I Barry, Hiroyuki Nakamura
  • Publication number: 20230099440
    Abstract: A piezoelectric microelectromechanical systems device is provided, having a first piezoelectric layer, a first metal layer including a first metal, a second metal layer including a second metal, the first and second metals having different properties to compensate deflection due to thermal stress of any or all of the piezoelectric layer, the first metal layer, and second metal layer and a substrate including at least one wall defining a cavity and the at least one wall supporting the layers. The method for making the piezoelectric microelectromechanical systems device is also provided.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 30, 2023
    Inventors: Siarhei Dmitrievich Barsukou, Myeong Gweon Gu, Hiroyuki Nakamura
  • Publication number: 20230094674
    Abstract: A system for compensating for thermal stress in piezoelectric microelectromechanical systems devices can have a piezoelectric layer at least partially spanning a cavity such that it generates electrical signals when external forces cause the piezoelectric layer to vibrate with respect to the cavity. At least one electrode layer can include a conductive metal positioned adjacent the piezoelectric layer and configured as an electrode to accept the electrical signals. The piezoelectric layer and electrode layer can have an expected thermal stress tending to cause expected deflection even when external forces are not causing the piezoelectric layer to vibrate. A compensation layer can be positioned adjacent at least one of the piezoelectric layer and the at least one electrode layer and configured to counteract the expected deflection from the expected thermal stress.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 30, 2023
    Inventors: Siarhei Dmitrievich Barsukou, Myeong Gweon Gu, Hiroyuki Nakamura
  • Patent number: 11616487
    Abstract: Aspects of this disclosure relate to acoustic wave devices on stacked die. A first die can include first acoustic wave device configured to generate a boundary acoustic wave. A second die can include a second acoustic wave device configured to generate a second boundary acoustic wave, in which the second die is stacked with the first die. The first acoustic wave resonator can include a piezoelectric layer, an interdigital transducer electrode on the piezoelectric layer, and high acoustic velocity layers on opposing sides of the piezoelectric layer. The high acoustic velocity layers can each have an acoustic velocity that is greater than a velocity of the boundary acoustic wave.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: March 28, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventors: Hiroyuki Nakamura, Rei Goto, Keiichi Maki
  • Patent number: 11616491
    Abstract: Aspects of this disclosure relate to a surface acoustic wave device. The surface acoustic wave device includes a piezoelectric layer and an interdigital transducer. The interdigital transducer electrode includes a pair of electrodes, each electrode having a bus bar and fingers extending from the bus bar. The interdigital transducer electrode has an interdigital region defined by a portion of the fingers of the electrodes that interdigitate with each other. A dielectric layer is disposed over the interdigital transducer electrode outside the interdigital region and configured to reduce a loss of the surface acoustic wave device.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: March 28, 2023
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Gong Bin Tang, Rei Goto, Hiroyuki Nakamura
  • Patent number: 11610882
    Abstract: A semiconductor device includes a semiconductor substrate in which a first region having a freewheeling diode arranged therein, second regions having an IGBT arranged therein, and a withstand-voltage retention region surrounding the first region and the second regions in plan view are defined. The semiconductor substrate has a first main surface and a second main surface. The semiconductor substrate includes an anode layer having a first conductivity type, which is arranged in the first main surface of the first region, and a diffusion layer having the first conductivity type, which is arranged in the first main surface of the withstand-voltage retention region adjacently to the anode layer. A first trench is arranged in the first main surface on a side of the anode layer with respect to a boundary between the anode layer and the diffusion layer.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: March 21, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroyuki Nakamura, Shinya Soneda
  • Patent number: 11595935
    Abstract: In a wireless information collecting method executed by at least one user terminal device that measures wireless information used in a site survey and a server device that stores the wireless information and performs the site survey, the user terminal device performs a step of periodically measuring a current position and transmitting positioning information indicating the current position to the server device, and a step of measuring the wireless information in accordance with a wireless information measurement number instructed by the server device and transmitting wireless information including a position and time to the server device.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 28, 2023
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Tomoaki Ogawa, Hiroyuki Nakamura, Shinya Otsuki, Makoto Umeuchi, Junichi Iwatani, Hiroshi Sakamoto, Masayoshi Nabeshima
  • Publication number: 20230031568
    Abstract: An acoustic wave resonator comprises a carrier substrate, a layer of dielectric material disposed on an upper surface of the carrier substrate, and a layer of piezoelectric material disposed above the layer of dielectric material. The layer of piezoelectric material includes a pair of opposing terminating edges that are coterminous with the layer of dielectric material. One or more interdigital transducers (IDTs) are disposed on the layer of piezoelectric material. The opposing terminating edges sandwich the one or more interdigital transducers, and in some examples, a pair of reflector gratings disposed on the layer of piezoelectric material and each including less than eight reflector fingers. The opposing terminating edges provide edge reflections that allow a reduction in size or a complete removal of the reflector gratings, resulting in a smaller acoustic wave resonator compared to conventional devices while maintaining a comparable performance.
    Type: Application
    Filed: July 21, 2022
    Publication date: February 2, 2023
    Inventors: Gong Bin Tang, Rei Goto, Hironori Fukuhara, Keiichi Maki, Hiroyuki Nakamura
  • Publication number: 20230028753
    Abstract: A semiconductor apparatus includes: a semiconductor substrate; a diffusion layer; a first depletion prevention region; a channel stopper electrode, a monitor electrode and an insulating film. The inner edge portion of the monitor electrode is positioned between the diffusion layer and the first depletion prevention region. A distance between the outer edge portion of the channel stopper electrode and the inner edge portion of the monitor electrode is a first distance. A distance between the diffusion layer and the first depletion prevention region is a second distance. The first and second distances are set so that a discharge voltage between the channel stopper electrode and the monitor electrode becomes greater than an avalanche breakdown voltage at a PN junction portion of the diffusion layer and the semiconductor substrate.
    Type: Application
    Filed: October 4, 2022
    Publication date: January 26, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hiroyuki NAKAMURA, Kazutoyo TAKANO
  • Patent number: 11560004
    Abstract: A liquid ejection apparatus includes a liquid ejection head that is detachably attached and ejects a liquid, and a control section that is configured to transmit a delivery request for a new liquid ejection head to a server apparatus via a network.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: January 24, 2023
    Assignee: Seiko Epson Corporation
    Inventors: Hiroyuki Nakamura, Izumi Nozawa, Yuta Komatsu
  • Publication number: 20220411368
    Abstract: A benzoic acid salt of 4-[5-[(3S)-3-aminopyrrolidine-1-carbonyl]-2-[2-fluoro-4-(2-hydroxy-2-methyl-propyl)phenyl]phenyl]-2-fluoro-benzonitrile is provided. A sorbic acid salt of 4-[5-[(3S)-3-aminopyrrolidine-1-carbonyl]-2-[2-fluoro-4-(2-hydroxy-2-methyl-propyl)phenyl]phenyl]-2-fluoro-benzonitrile is also provided.
    Type: Application
    Filed: November 13, 2020
    Publication date: December 29, 2022
    Inventor: Hiroyuki NAKAMURA
  • Publication number: 20220407496
    Abstract: A acoustic wave resonator comprises a piezoelectric substrate and a plurality of interdigital transducer (IDT) electrodes disposed on the piezoelectric substrate, the plurality of IDT electrodes formed of a mixture of tungsten and chromium to provide for reduction in size and increase in quality factor of the acoustic wave resonator.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 22, 2022
    Inventors: Michael David Hill, Benjamin Paul Abbott, Yosuke Hamaoka, Hiroyuki Nakamura, Alan Sangone Chen
  • Patent number: 11531053
    Abstract: Provided is a semiconductor device that can detect the cracking progress with high precision. A semiconductor device is formed using a semiconductor substrate, and includes an active region in which a semiconductor element is formed, and an edge termination region outside the active region. A crack detection structure is termed in the edge termination region of the semiconductor substrate. The crack detection structure includes: a trench formed in the semiconductor substrate and extending in a circumferential direction of the edge termination region; an inner-wall insulating film formed on an inner wall of the trench; an embedded electrode formed on the inner-wall insulating film and embedded into the trench; and a monitor electrode formed on the semiconductor substrate and connected to the embedded electrode.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: December 20, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazutoyo Takano, Hiroyuki Nakamura
  • Patent number: D978831
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: February 21, 2023
    Assignee: Canon Denshi Kabushiki Kaisha
    Inventors: Masaaki Ishibashi, Masahiro Kando, Tsutomu Yoshihara, Minoru Tsuruta, Hiroyuki Nakamura