Abstract: An electromagnetic relay includes a fixed contact, a movable contact, a movable contact piece, a movable iron core, a drive shaft, a coil, and a stopper. The movable iron core is movable in a moving direction including a contact direction in which the movable contact approaches the fixed contact and a separation direction in which the movable contact separates from the fixed contact. The movable iron core includes a shaft hole extending in the moving direction. The drive shaft is connected to the movable contact piece. The drive shaft extends through the shaft hole. The drive shaft is fixed to the movable iron core. The coil generates a magnetic force to move the movable iron core in the moving direction. The stopper is connected to the drive shaft. The stopper restricts a movement of the movable iron core with respect to the drive shaft in the moving direction.

Abstract: The electromagnetic relay includes a fixed terminal, a fixed contact connected to the fixed terminal, a movable contact piece moving in an opening direction and a closing direction with respect to the fixed terminal, a movable contact connected to the movable contact piece and being arranged to face the fixed contact, a coil generating an electromagnetic force to move the movable contact piece, and a drive circuit controlling a current to the coil. The drive circuit increases the current at a first increase rate in a first period that includes a period from a start time when the current starts to flow in the coil to before a contact time point at which the movable contact contacts the fixed contact. The drive circuit increases the current at a second increase rate larger than the first increase rate in the second period that includes a period after the contact time point.

Abstract: A method of forming a three-dimensional semiconductor device includes forming an alternating stack of insulating layers and spacer material layers over a substrate, forming memory openings formed in the memory array region and monitor openings formed in a monitor region though the alternating stack, forming memory opening fill structures in the memory openings, forming monitor opening fill structures by depositing a monitor opening fill material in the monitor openings, recessing first portions of the alternating stack in a contact region and second portions of the alternating stack in the monitor region, and determining at least one characteristic of the recessed surfaces of the monitor opening fill structures. At least one characteristic of the memory openings or memory opening fill structures may be determined based on the determining at least one characteristic of the recessed surfaces of the monitor opening fill structures.

Abstract: A semiconductor structure includes a memory array including first and second bit lines and a sense amplifier circuit. The sense amplifier circuit includes a first sense amplifier array containing first active sense amplifier transistors that each have an active region having a first width, where the first active sense amplifier transistors are electrically connected to the first bit lines, and a second sense amplifier array including second active sense amplifier transistors that each have the active region having the first width, where the second active sense amplifier transistors are electrically connected to the second bit lines, and dummy active regions which are electrically inactive located between columns of the second active sense amplifier transistors.

Abstract: A method of manufacturing monocrystalline silicon is provided, the method including pulling monocrystalline silicon out of a silicon melt by a Czochralski process, the silicon melt being stored in a crucible housed in a chamber, the silicon melt being added with a volatile dopant, in which a decompression rate ES for exhaust of a gas out of the chamber before the pulling of the monocrystalline silicon is within a range below at least until a pressure inside the chamber decreases from an atmospheric pressure to 80 kPa, 0 kPa/min<ES?4.2 kPa/min.

Abstract: An electromagnetic relay includes a fixed contact, a movable contact, a movable contact piece, a case, and an adhesive material. The movable contact is disposed to face the fixed contact. The movable contact piece is connected to the movable contact. The movable contact piece is movable between a closed position in which the movable contact is in contact with the fixed contact and an open position in which the movable contact is separated from the fixed contact. The case accommodates the fixed contact and the movable contact. The adhesive material is disposed in the case. The adhesive material captures foreign matter in the case.

Abstract: A bonded assembly includes a first memory die and a logic die. The first memory die includes a first alternating stack of first insulating layers and first electrically conductive layers, first memory opening fill structures, a first stepped dielectric material portion, and first column-shaped conductive via structures including a respective conductive shaft portion vertically extending through a respective subset of the first electrically conductive layers, a respective conductive base portion, and a respective conductive capital portion contacting a horizontal surface of a respective one of the first electrically conductive layers. The logic die includes logic-side bonding pads that are bonded to the first column-shaped conductive via structures.

Abstract: The flow rate control device 10 includes a control valve 11, a restriction part 12 provided downstream of the control valve 11, an upstream pressure sensor 13 for measuring a pressure P1 between the control valve 11 and the restriction part 12, a differential pressure sensor 20 for measuring a differential pressure ?P between the upstream and the downstream of the restriction part 12, and an arithmetic control circuit 16 connected to the control valve 11, the upstream pressure sensor 13, and the differential pressure sensor 20.

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over at least one source layer, and groups of memory opening fill structures vertically extending through the alternating stack. Each memory opening fill structure can include a vertical stack of memory elements and a vertical semiconductor channel. A plurality of source-side select gate electrodes can be laterally spaced apart by source-select-level dielectric isolation structures. Alternatively or additionally, the at least one source layer may include a plurality of source layers. A group of memory opening fill structures can be selected by selecting a source layer and/or by selecting a source-level electrically conductive layer.

Abstract: A bonded assembly includes a memory die containing a three-dimensional memory array, a first logic die bonded to the memory die, a first peripheral circuit located in the logic die and configured to control operation of a first set of electrical nodes of the three-dimensional memory array, and a second peripheral circuit configured to control operation of a second set of electrical nodes of the three-dimensional memory array, where the second peripheral circuit is located at a different vertical level than the first peripheral circuit relative to the three-dimensional-memory array.

Abstract: A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Source/drain implantation is conducted using the gate strip as a mask. The gate strip is divided into gate electrodes after the implantation.

Abstract: A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

Abstract: An electric motor includes: a stator including stator coils; and a rotor arranged outside the stator. Further, a plurality of fins is provided at a position, which faces the stator coils, on an inner surface of the rotor.

Abstract: A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Source/drain implantation is conducted using the gate strip as a mask. The gate strip is divided into gate electrodes after the implantation.

Abstract: A semiconductor structure includes a memory array including first and second bit lines and a sense amplifier circuit. The sense amplifier circuit includes a first sense amplifier array containing first active sense amplifier transistors that each have an active region having a first width, where the first active sense amplifier transistors are electrically connected to the first bit lines, and a second sense amplifier array including second active sense amplifier transistors that each have the active region having the first width, where the second active sense amplifier transistors are electrically connected to the second bit lines, and dummy active regions which are electrically inactive located between columns of the second active sense amplifier transistors.

Abstract: A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Deep source/drain regions are formed by implanting dopants into semiconductor active regions without implanting the dopants into inter-electrode regions of a shallow trench isolation structure. The gate strip is divided into gate stacks prior to or after formation of the deep source/drain regions.

Abstract: A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Source/drain implantation is conducted using the gate strip as a mask. The gate strip is divided into gate electrodes after the implantation.

Abstract: A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Source/drain implantation is conducted using the gate strip as a mask. The gate strip is divided into gate electrodes after the implantation.