Abstract: There is provided a liquid ejecting apparatus including: a head having a nozzle surface in which a nozzle is opened; a wiper configured to move relative to the head in a state that the wiper is in contact with the nozzle surface; and a controller. The controller is configured to move the wiper relative to the head based on a moving velocity determined based on parameters including first parameter according to a receding contact angle of a liquid to be discharged from the nozzle and second parameter according to a viscosity of the liquid.

Abstract: A cylindrical inner wall used in a substrate processing apparatus and surrounding a stage on which a substrate is placed, with a gap between the inner wall and an outer periphery of the stage. The inner wall includes a plurality of slits formed in a lower end of the inner wall, and a plurality of grooves formed in the inner surface of the inner wall to extend from an upper end to the lower end of the inner wall so as to communicate with the slits.

Abstract: A processing apparatus includes a processor. The processor acquires an image in which region marker information of a lesion is set with respect to an ultrasonic image of an ultrasonic endoscope with a biopsy needle, and calculates an angle of the biopsy needle for inserting the biopsy needle into the lesion based on a movable range of the biopsy needle and the region marker information.

Abstract: A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.

Abstract: An electromagnetic relay includes a fixed contact, a movable contact piece, a movable contact, a contact case, a drive device, and an elastic member. The movable contact is disposed to face the fixed contact. The movable contact piece is connected to the movable contact. The movable contact piece is configured to move in an opening direction and a closing direction. The contact case houses the fixed contact, the movable contact, and the movable contact piece. The drive device includes a coil. The coil generates an electromagnetic force that moves the movable contact piece. The elastic member is disposed between the drive device and the contact case. The elastic member seals between the drive device and the contact case.

Abstract: There are provided a plurality of radio devices detecting an interference source signal transmitted by an interference source and generating pieces of air time information showing whether the interference source signal exists or not for each predetermined time unit; and an aggregation device estimating air time of the interference source by acquiring the pieces of air time information from the plurality of radio devices and aggregating/integrating the acquired pieces of air time information for each predetermined unit time, matching timings.

Abstract: An object of the present invention is to provide an anti-BMP10 antibody, and a therapeutic agent for hypertension and a hypertensive disease, containing the antibody as an active ingredient. The present invention relates to an anti-BMP10 monoclonal antibody or an antibody fragment thereof that binds to human BMP10 (bone morphogenetic protein 10). Further, the present invention relates to a therapeutic agent for hypertension and a hypertensive disease containing an antagonist for at least one of BMP10 and a BMP9/BMP10 heterodimer, a diagnostic agent or a pharmaceutical composition for a disease associated with human BMP10, an immunological detection method or a measurement method for human BMP10 using the antagonist, and use of the antagonist for producing a pharmaceutical composition for treating hypertension and a hypertensive disease.

Abstract: A non-clogging pump includes a pump casing and an impeller that includes a main plate portion and a vane portion, in which the main plate portion includes a main plate protrusion portion that protrudes in a counter-inflow direction, the vane portion includes a first end face and a second end face and is connected to the main plate protrusion portion at an inner periphery-side end portion, and an inner peripheral wall that forms the suction port of the pump casing includes a suction port protrusion portion that is provided at a portion in a rotation direction of the rotating shaft, is disposed along the second end face with a gap from the second end face, and protrudes toward a center side of the suction port.

Abstract: A predetermined radio base station and subordinate radio terminals detect signals (beacons) regularly transmitted by other radio base stations, transmit information about radio channels and base station identifiers of the detected signals, and position information about the radio terminals to an interference area detection device to aggregate the information and the position information as a base station-base station detection list and a terminal-base station detection list.

Abstract: A method of manufacturing a light control element including an extraction electrode portion includes the steps of obtaining a light control film including a first base material with a transparent electrode layer and a second base material with a transparent electrode layer arranged so that transparent electrode layers are opposed to each other, a liquid crystal light control layer sandwiched between the base materials with transparent electrode layers, and an extending portion extending in a direction perpendicular to a thickness direction; inserting peeling means between the base materials with transparent electrode layers in the extending portion, to thereby peel off one base material with a transparent electrode layer from the light control film and bending a peeled portion of the one base material with a transparent electrode layer outward, to snap the peeled portion. The one base material has a breakage bending diameter of from 0.1 mm to 5 mm.

Abstract: A cylindrical inner wall used in a substrate processing apparatus and surrounding a stage on which a substrate is placed, with a gap between the inner wall and an outer periphery of the stage. The inner wall includes a plurality of slits formed in a lower end of the inner wall, and a plurality of grooves formed in the inner surface of the inner wall to extend from an upper end to the lower end of the inner wall so as to communicate with the slits.

Abstract: A first field effect transistor contains a first active region including a source region, a drain region and a channel region located between the source region and the drain region, a first gate dielectric overlying the active region, and a first gate electrode overlying the first gate dielectric. A second field effect transistor contains a second active region including a source region, a drain region and a channel region located between the source region and the drain region, a second gate dielectric overlying the active region, a second gate electrode overlying the second gate dielectric. A trench isolation region surrounds the first and the second active regions. The first field effect transistor includes a fringe region in which the first gate electrode extends past the active region perpendicular to the source region to drain region direction and the second field effect transistor does not include the fringe region.

Abstract: A memory system is described having an x-direction (bit line direction) divided sub-block mode. Each block is divided in a y-direction and in the x-direction into a number of groups of contiguous NAND strings that are referred to as XY sub-blocks. The memory system performs a memory operation in parallel in multiple XY sub-blocks in a block while inhibiting the memory operation in the other XY sub-blocks in the block. Each XY sub-block for which the memory operation is performed has its NAND strings connected to a different set of contiguous bit lines. In an aspect the memory operation is a program operation with selected memory cells in each of the multiple XY sub-blocks programmed in parallel while inhibiting programming of all memory cells in all other XY sub-blocks in the block. In one aspect, the memory operation is an erase operation.

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures including a vertical channel and memory elements located in the memory openings, a contact via cavity vertically extending through the alternating stack, and an integrated contact-and-support assembly located in the contact via cavity. The integrated contact-and-support assembly includes a dielectric support pillar and a conductive layer contact via structure electrically contacting a top surface of a first electrically conductive layer of the electrically conductive layers that surrounds the contact via cavity. A dielectric spacer is located in the contact via cavity, covering a sidewall of the first electrically conductive layer in the contact via cavity, and extending above the top surface of the first electrically conductive layer.

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips, backside trenches located between neighboring pairs of alternating stacks, memory openings vertically extending through the alternating stacks, and memory opening fill structures located within the memory openings. In some embodiments, dielectric etch stop structures may be located within or outside the backside trenches such that each of the dielectric etch stop structures includes a respective pair of dielectric sidewalls that are located within a pair of lengthwise sidewalls of the respective one of the backside trenches. In some other embodiments, a dielectric isolation structure can laterally contact each of the insulating strips within the alternating stacks. Laterally insulated contact via structures can be provided to provide electrical contact to a respective one of the electrically conductive strips.

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips, backside trenches located between neighboring pairs of alternating stacks, memory openings vertically extending through the alternating stacks, and memory opening fill structures located within the memory openings. In some embodiments, dielectric etch stop structures may be located within or outside the backside trenches such that each of the dielectric etch stop structures includes a respective pair of dielectric sidewalls that are located within a pair of lengthwise sidewalls of the respective one of the backside trenches. In some other embodiments, a dielectric isolation structure can laterally contact each of the insulating strips within the alternating stacks. Laterally insulated contact via structures can be provided to provide electrical contact to a respective one of the electrically conductive strips.

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory cells. An integrated line-and-via structure is provided, which is a unitary structure including a metallic plate portion that is a portion of or laterally contacts an electrically conductive layer, and a metallic via portion that vertically extends through dielectric material plates that overlie the metallic plate portion.

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory cells. An integrated line-and-via structure is provided, which is a unitary structure including a metallic plate portion that is a portion of or laterally contacts an electrically conductive layer, and a metallic via portion that vertically extends through dielectric material plates that overlie the metallic plate portion.

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers, and memory stack structures vertically extending through a respective one of the alternating stacks and located within the first memory array region and the second memory array region. An inter-array region containing lower and upper staircases is located between the first and the second memory array regions. The first memory array region may have a greater length than the second memory array region, or the lower staircase may generally ascend in an opposite direction from the upper staircase.