Patents by Inventor Hiroyuki Shindo

Hiroyuki Shindo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10989794
    Abstract: Scanning optical system, comprising a rotatable mirror unit including first and second mirror surfaces each inclining relative to a rotation axis, and a light projecting system including a light source which emits light flux toward an object through the mirror unit. The light flux is reflected on the first mirror surface, then to the second mirror surface, and projected so as to scan on the object correspondingly to rotation of the mirror unit. The mirror unit includes multiples pairs of the first and second mirror surfaces, and the respective intersection angles of the multiples pairs are different from each other. In one rotation of the mirror unit, light flux emitted from the light source is reflected on the second mirror surfaces, and is projected sequentially, thereby to scan a measurement range in which the object is measured. Length in a sub scanning direction of the light flux and intersection angles of the multiples pairs correspond to length in a sub scanning direction of the measurement range.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: April 27, 2021
    Assignee: Konica Minolta, Inc.
    Inventors: Ryouta Ishikawa, Hiroyuki Matsuda, Masashi Kageyama, Junichiro Yonetake, Hideyuki Fujii, Hiroyuki Shindo
  • Publication number: 20210080485
    Abstract: This invention is directed to a pattern height information correction system which includes a contour line information of a pattern extracted from an acquired image including at least an AFM (atomic force microscope) module, a design information database that stores design information including at least layer information, and a computer system that divides the extracted pattern into regions based on the design information stored in the design information database relating to the extracted pattern and associates the divided regions with layer information, in which the computer system specifies a horizontal region designated as horizontal in advance from the divided regions, creates an approximated curved surface based on the specified horizontal region corresponding to the same layer information, and corrects height information of the extracted pattern using the approximated curved surface.
    Type: Application
    Filed: August 4, 2020
    Publication date: March 18, 2021
    Inventors: Kenji YAMASAKI, Hiroyuki SHINDO, Taeko KASHIWA, Ryugo KAGETANI
  • Patent number: 10937146
    Abstract: The image evaluation device includes a design data image generation unit that images design data; a machine learning unit that creates a model for generating a design data image from an inspection target image, using the design data image as a teacher and using the inspection target image corresponding to the design data image; a design data prediction image generation unit that predicts the design data image from the inspection target image, using the model created by the machine learning unit; a design data image generation unit that images the design data corresponding to the inspection target image; and a comparison unit that compares a design data prediction image generated by the design data prediction image generation unit and the design data image. As a result, it is possible to detect a systematic defect without using a defect image and generating misinformation frequently.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: March 2, 2021
    Assignee: Hitachi High-Tech Corporation
    Inventors: Shinichi Shinoda, Masayoshi Ishikawa, Yasutaka Toyoda, Yuichi Abe, Hiroyuki Shindo
  • Patent number: 10718611
    Abstract: The present invention provides a semiconductor evaluation device for fabricating a suitable reference pattern utilized in comparison tests. The semiconductor evaluation device and computer program extract a process window in a more accurate range based on a two-dimensional evaluation of the pattern. In order to achieve the above described objects, the present invention includes a semiconductor evaluation device that measures the dimensions of the pattern formed over the sample based on a signal obtained by way of a charged particle beam device, selects a pattern whose dimensional measurement results satisfy specified conditions or exposure conditions when the pattern is formed, and forms synthesized contour data, by synthesizing contour data obtained from images of an identically shaped pattern in design data, and also a pattern formed under the selected exposure conditions or a pattern having a positional relation that is already known relative to the selected pattern.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: July 21, 2020
    Assignee: Hitachi High-Tech Corporation
    Inventors: Asuka Honda, Hiroyuki Shindo
  • Publication number: 20200134355
    Abstract: An object of the present invention is to achieve both suppression of data amount of an image processing system that learns a collation image to be used for image identification using a discriminator and improvement of identification performance of the discriminator. In order to achieve the above object, there is proposed an image processing system including a discriminator that identifies an image using a collation image, the image processing system further including a machine learning engine that performs machine learning of collation image data required for image identification. The machine learning engine searches for a successfully identified image using an image for which identification has been failed, and adds information, obtained based on a partial image of the image for which identification has been failed and which has been selected by an input device to the successfully identified image obtained by the search to generate corrected collation image data.
    Type: Application
    Filed: March 15, 2018
    Publication date: April 30, 2020
    Inventors: Shinichi SHINODA, Yasutaka TOYODA, Shigetoshi SAKIMURA, Masayoshi ISHIKAWA, Hiroyuki SHINDO, Hitoshi SUGAHARA
  • Publication number: 20200074611
    Abstract: A pattern inspection system inspects an image of an inspection target pattern of an electronic device using an identifier constituted by machine learning, based on the image of the inspection target pattern of the electronic device and data used to manufacture the inspection target pattern. The system includes a storage unit which stores a plurality of pattern images of the electronic device and pattern data used to manufacture a pattern of the electronic device, and an image selection unit which selects a learning pattern image used in the machine learning from the plurality of pattern images, based on the pattern data and the pattern image stored in the storage unit.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 5, 2020
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Shuyang DOU, Shinichi SHINODA, Yasutaka TOYODA, Hiroyuki SHINDO
  • Publication number: 20200033122
    Abstract: The present invention is intended to provide a pattern evaluation apparatus and a computer program aimed at achieving defect inspection with high efficiency and high precision while allowing manufacturing variations that are dissimilar depending on the sites of a circuit. In order to achieve the above object, proposed are a computer program and an inspection system having a means of performing statistical processing of measurement data of a plurality of inspection target patterns having similar or same design pattern shape used for manufacturing the inspection target patterns, and performing adjustment of a defect determination threshold in accordance with a distribution state of measurement data.
    Type: Application
    Filed: August 4, 2017
    Publication date: January 30, 2020
    Inventors: Yasutaka TOYODA, Hiroyuki SHINDO
  • Patent number: 10445875
    Abstract: A pattern-measuring apparatus and a semiconductor-measuring system are provided which are able to obtain an evaluation result for suitably selecting processing with respect to a semiconductor device. In particular, there is proposed a pattern-measuring apparatus including an arithmetic device which compares a circuit pattern of an electronic device with a reference pattern, in which the arithmetic device classifies the circuit pattern in processing unit of the circuit pattern on the basis of a comparison of a measurement result between the circuit pattern and the reference pattern with at least two threshold values.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 15, 2019
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yasutaka Toyoda, Norio Hasegawa, Takeshi Kato, Hitoshi Sugahara, Yutaka Hojo, Daisuke Hibino, Hiroyuki Shindo
  • Publication number: 20190228522
    Abstract: The image evaluation device includes a design data image generation unit that images design data; a machine learning unit that creates a model for generating a design data image from an inspection target image, using the design data image as a teacher and using the inspection target image corresponding to the design data image; a design data prediction image generation unit that predicts the design data image from the inspection target image, using the model created by the machine learning unit; a design data image generation unit that images the design data corresponding to the inspection target image; and a comparison unit that compares a design data prediction image generated by the design data prediction image generation unit and the design data image. As a result, it is possible to detect a systematic defect without using a defect image and generating misinformation frequently.
    Type: Application
    Filed: January 18, 2019
    Publication date: July 25, 2019
    Inventors: Shinichi SHINODA, Masayoshi ISHIKAWA, Yasutaka TOYODA, Yuichi ABE, Hiroyuki SHINDO
  • Publication number: 20190056481
    Abstract: Scanning optical system, comprising a rotatable mirror unit including first and second mirror surfaces each inclining relative to a rotation axis, and a light projecting system including a light source which emits light flux toward an object through the mirror unit. The light flux is reflected on the first mirror surface, then to the second mirror surface, and projected so as to scan on the object correspondingly to rotation of the mirror unit. The mirror unit includes multiples pairs of the first and second mirror surfaces, and the respective intersection angles of the multiples pairs are different from each other. In one rotation of the mirror unit, light flux emitted from the light source is reflected on the second mirror surfaces, and is projected sequentially, thereby to scan a measurement range in which the object is measured. Length in a sub scanning direction of the light flux and intersection angles of the multiples pairs correspond to length in a sub scanning direction of the measurement range.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 21, 2019
    Inventors: Ryouta ISHIKAWA, Hiroyuki MATSUDA, Masashi KAGEYAMA, Junichiro YONETAKE, Hideyuki FUJII, Hiroyuki SHINDO
  • Patent number: 10078132
    Abstract: The present invention provides a scanning optical system and radar that can suppress longitudinal distortion and spot rotation of a spot light radiated on an object. A light flux emitted from a light source is reflected on a first mirror surface of a mirror unit, then, proceeds to a second mirror surface, further is reflected on the second mirror surface, and is projected so as to scan on an object correspondingly to rotation of the mirror unit. The light flux emitted from the light projecting system is made longer in a sub scanning angle direction than in a scanning angle direction in a measurement range of the object and satisfies the following conditional expression, |?1?90|×|?|?255 . . . (1); in the expression, ?1 is an intersection angle (°) between the first mirror surface and the second mirror surface, and ? is a rotation angle (°).
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: September 18, 2018
    Assignee: Konica Minolta, Inc.
    Inventors: Ryouta Ishikawa, Hiroyuki Matsuda, Masashi Kageyama, Junichiro Yonetake, Hideyuki Fujii, Hiroyuki Shindo
  • Publication number: 20180247400
    Abstract: A pattern-measuring apparatus and a semiconductor-measuring system are provided which are able to obtain an evaluation result for suitably selecting processing with respect to a semiconductor device. In particular, there is proposed a pattern-measuring apparatus including an arithmetic device which compares a circuit pattern of an electronic device with a reference pattern, in which the arithmetic device classifies the circuit pattern in processing unit of the circuit pattern on the basis of a comparison of a measurement result between the circuit pattern and the reference pattern with at least two threshold values.
    Type: Application
    Filed: April 27, 2018
    Publication date: August 30, 2018
    Inventors: Yasutaka TOYODA, Norio HASEGAWA, Takeshi KATO, Hitoshi SUGAHARA, Yutaka HOJO, Daisuke HIBINO, Hiroyuki SHINDO
  • Patent number: 9990708
    Abstract: An object of the present invention is to provide a pattern-measuring apparatus and a semiconductor-measuring system which are able to obtain an evaluation result for suitably selecting processing with respect to a semiconductor device. In the present invention for attaining the object described above, there is proposed a pattern-measuring apparatus including an arithmetic device which compares a circuit pattern of an electronic device with a reference pattern, in which the arithmetic device classifies the circuit pattern in processing unit of the circuit pattern on the basis of a comparison of a measurement result between the circuit pattern and the reference pattern with at least two threshold values.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: June 5, 2018
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yasutaka Toyoda, Norio Hasegawa, Takeshi Kato, Hitoshi Sugahara, Yutaka Hojo, Daisuke Hibino, Hiroyuki Shindo
  • Publication number: 20180108875
    Abstract: A patterning apparatus contains a UV ray generating unit; a housing that reflects and guides UV rays generated from the UV ray generating unit; and a glass mask to be irradiated with the UV rays, the glass mask being located below the housing, in which the patterning apparatus is provided with a pair of air flow generation units at opposing positions of an upper surface of the glass mask so that air is blown in parallel to the glass mask and in a direction toward a center of the glass mask through a gap between the glass mask and the housing.
    Type: Application
    Filed: October 6, 2015
    Publication date: April 19, 2018
    Inventors: Naohiro OKUMURA, Hiroyuki SHINDO, Masahiro MORIKAWA
  • Patent number: 9869856
    Abstract: An illumination device including a light source device, a rotary diffusion plate, which includes a first surface, a second surface, a diffusion section disposed on the first surface, and a detection section disposed on at least one of the first surface and the second surface, and to which light from the light source device is input, a light collecting optical system to which light from the diffusion section is input, a detector adapted to detect light from the detection section, and a control device adapted to control the light source device in accordance with a signal output from the detector. The detection section is disposed at a position different from a position where the light from the light source device enters the diffusion section.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: January 16, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Nozomu Inoue, Akira Miyamae, Shigehiro Yanase, Hiroyuki Shindo
  • Patent number: 9858659
    Abstract: Provided is a pattern inspecting and measuring device that decreases the influence of noise and the like and increases the reliability of an inspection or measurement result during inspection or measurement using the position of an edge extracted from image data obtained by imaging a pattern as the object of inspection or measurement. For this purpose, in the pattern inspecting and measuring device in which inspection or measurement of an inspection or measurement object pattern is performed using the position of the edge extracted, with the use of an edge extraction parameter, from the image data obtained by imaging the inspection or measurement object pattern, the edge extraction parameter is generated using a reference pattern having a shape as an inspection or measurement reference and the image data.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: January 2, 2018
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Tsuyoshi Minakawa, Takashi Hiroi, Takeyuki Yoshida, Taku Ninomiya, Takuma Yamamoto, Hiroyuki Shindo, Fumihiko Fukunaga, Yasutaka Toyoda, Shinichi Shinoda
  • Patent number: 9846931
    Abstract: An object of the invention is to provide a pattern measuring device for generating appropriate reference pattern data while suppressing an increase in the manufacturing cost that would occur when manufacturing conditions are finely changed. A pattern measuring device has an arithmetic processing unit for measuring a pattern formed on a sample. The arithmetic processing unit, on the basis of signals obtained with a charged particle beam device, acquires or generates image data or contour line data on a plurality of circuit patterns created under different manufacturing conditions of a manufacturing apparatus, and generates reference data to be used for measurement of a circuit pattern from the image data or contour line data.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: December 19, 2017
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yasutaka Toyoda, Hiroyuki Shindo, Yoshihiro Ota
  • Patent number: 9816958
    Abstract: It is an object of the present invention to provide a NOx sensor for accurately obtaining the resistance value of a heater. When a second layer is laminated immediately above a first layer on which the heater for electrically heating the proximity of an inner space of the NOx sensor and two heater leads having substantially same shape which are energizing paths to the heater are formed, the second layer on which at least one of leads is formed out of a first lead for electrically connecting a reference electrode to outside, a second lead for electrically connecting a measuring electrode to outside, and a third lead for electrically connecting a plurality of pump electrodes to outside, the lead formed on the second layer is arranged so as not to overlap any of two heater leads in a laminating direction of the first layer and the second layer.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: November 14, 2017
    Assignee: NGK Insulators, Ltd.
    Inventors: Hiroki Fujita, Hiroyuki Shindo
  • Patent number: 9755191
    Abstract: Disclosed is a method for manufacturing an organic EL element, which has, on a supporting substrate, at least one intermediate electrode layer, and at least two light emitting units, each of which has one or a plurality of organic functional layers, the intermediate electrode layer being disposed between the light emitting units. The method is characterized in having: a first patterning step wherein at least one organic functional layer of each of the light emitting units is patterned using a mask; and a second patterning step wherein at least one organic functional layer in each of the light emitting units is patterned into, by means of light irradiation, a region where a light emitting function is modulated, and a region where the light emitting function is not modulated. The method is also characterized in that the second patterning step is performed for each light emitting unit that is manufactured.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: September 5, 2017
    Assignee: Konica Minolta, Inc.
    Inventors: Kuniaki Uezawa, Masahiro Morikawa, Hiroyuki Shindo
  • Patent number: 9679371
    Abstract: In order to enable the computation of a process window including an arbitrary exposure condition, the present invention comprises: a contour data extraction means for extracting contour data from captured images of a plurality of circuit patterns formed by altering exposure conditions for identical design layouts; a shape variation measurement means for measuring, on the basis of the plurality of sets of extracted contour data, the amount of shape deformation at each edge or local region of the circuit patterns; a variation model computation means for computing, on the basis of the measured amount of shape deformation, a variation model for the contour data of a circuit pattern or a shape corresponding to a prescribed exposure condition; and a process window computation means using the variation model to estimate the amount of shape variation of a circuit pattern or a shape corresponding to an arbitrary exposure condition with respect to a circuit pattern or a shape corresponding to an exposure condition spec
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: June 13, 2017
    Assignee: Hitachi High-Technologies Corporation
    Inventor: Hiroyuki Shindo