Patents by Inventor Hiroyuki Tenmei

Hiroyuki Tenmei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6946723
    Abstract: A semiconductor device having a semiconductor element is obtained by cutting a semiconductor wafer, having an electrode pad formed on one side thereof, along a scribe line. The semiconductor device has a semiconductor element protective layer on the semiconductor element so as to form an opening above the pad, a stress cushioning layer on the layer so as to form an opening on the pad, a lead wire portion reaching the layer from the electrode pad via the openings, external electrodes on the lead wire portion, and a conductor protective layer on the layer. The layer, the layer, and the conductor protective layer form respective end faces on the end surface of the semiconductor element inside the scribe line and expose a surface of the semiconductor element from the end face of the end surface to a point inside of the scribe line, thereby to expose the scribe line.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: September 20, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Toshiya Satoh, Masahiko Ogino, Tadanori Segawa, Yoshihide Yamaguchi, Hiroyuki Tenmei, Atsushi Kazama, Ichiro Anjo, Asao Nishimura
  • Patent number: 6930388
    Abstract: A semiconductor device is provided which enables a flip chip connection without use of underfill. The semiconductor device includes a semiconductor element having circuit electrodes and a circuit surface coated with a protecting film. A stress relaxation layer is provided by coating a cured thermoplastic resin onto the protecting film of the circuit surface in a manner which leaves the circuit electrodes exposed and curing it and having an inclination in the edge portion thereof. A wiring layer with wirings is connected to each of the circuit electrodes and disposed so as to make an electrical connection from the circuit electrodes, via the edge portion of the stress relaxation layer, and to a desired portion on the surface of the stress relaxation layer. A protecting film is provided thereon, and an external connection terminal is also provided.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: August 16, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yoshihide Yamaguchi, Hiroyuki Tenmei, Kosuke Inoue, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Naoya Kanda, Madoka Minagawa, Ichiro Anjo, Asao Nishimura, Kenji Ujiie, Akira Yajima
  • Patent number: 6822317
    Abstract: A semiconductor apparatus comprising a semiconductor device, an electrically insulating layer formed on the semiconductor device, and an external connection terminal formed on the electrically insulating layer and electrically connected to an electrode of the semiconductor device, wherein a power/ground line and a signal line in a region of from an edge of the electrically insulating layer to a uniform-thickness flat portion of the electrically insulating layer are different in kind of wiring pattern from each other.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: November 23, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Kosuke Inoue, Hiroyuki Tenmei, Yoshihide Yamaguchi, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Madoka Minagawa, Naoya Kanda, Ichiro Anjo, Asao Nishimura, Akira Yajima, Kenji Ujiie
  • Publication number: 20040201105
    Abstract: The invention relates to a wiring board comprising a board having an electrode and being coated with an insulation layer with a hole for exposing the electrode; a wiring comprising a Cr or Ti layer, which is connected to the electrode and closely contacts with the insulation layer, and of a Cu layer which is closely contacts with the Cr or Ti layer; a protective film which covers the wiring and is provided with another hole for soldering; and a solder for the outer connection which is mounted in the both holes and brought to diffuse into the Cu layer to produce an alloy, and brought to reach the Cr or Ti layer thereby connecting the solder to the Cr or Ti layer.
    Type: Application
    Filed: April 27, 2004
    Publication date: October 14, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Yasunori Narizuka, Mitsuko Itou, Yoshihide Yamaguchi, Hiroyuki Tenmei
  • Publication number: 20040195687
    Abstract: A semiconductor apparatus in which flip chip bonding is enabled without any underfill, and which comprises a semiconductor device, an electrically insulating layer formed on the semiconductor device by mask-printing an electrically insulating material containing particles, and an external connection terminal formed on the electrically insulating layer and electrically connected with an electrode of the semiconductor device. The electrically insulating layer is formed with a thickness so as to provide &agr;-ray shielding of the semiconductor device.
    Type: Application
    Filed: April 16, 2004
    Publication date: October 7, 2004
    Inventors: Kosuke Inoue, Hiroyuki Tenmei, Yoshihide Yamaguchi, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Madoka Minagawa, Naoya Kanda, Ichiro Anjo, Asao Nishimura, Akira Yajima, Kenji Ujiie
  • Patent number: 6791178
    Abstract: A multi-chip module has semiconductor devices and a wiring substrate for mounting the semiconductor devices, in which the wiring substrate comprises a glass substrate having holes formed by sand blasting and a wiring layer formed on the surface of the glass substrate and having wiring and an insulation layer.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: September 14, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihide Yamaguchi, Takao Terabayashi, Hiroyuki Tenmei, Hiroshi Hozoji, Naoya Kanda
  • Patent number: 6780748
    Abstract: In the re-wiring formation process of a WLCSP, at least some of the re-wiring lines 3 that connect the bonding pads 1 and bump pads 2 of the semiconductor chips are formed using a photolithographic process that does not use a photomask. In this re-wiring formation process, standard portions are formed by development following photomask exposure, and portions that are to be designed corresponding to customer specifications are subjected to additional development following additional maskless exposure in the final stage.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: August 24, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihide Yamaguchi, Hiroyuki Tenmei, Hiroshi Hozoji, Naoya Kanda
  • Patent number: 6770547
    Abstract: A semiconductor apparatus in which flip chip bonding is enabled without any underfill, and which comprises a semiconductor device, an electrically insulating layer formed on the semiconductor device by mask-printing an electrically insulating material containing particles, and an external connection terminal formed on the electrically insulating layer and electrically connected with an electrode of the semiconductor device.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: August 3, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Kosuke Inoue, Hiroyuki Tenmei, Yoshihide Yamaguchi, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Madoka Minagawa, Naoya Kanda, Ichiro Anjo, Asao Nishimura, Akira Yajima, Kenji Ujiie
  • Patent number: 6756688
    Abstract: There are provided a high density and low manufacturing cost wiring board with high reliability in connection, a semiconductor device and a producing method therefor. The invention relates to a wiring board comprising a board having an electrode and being coated with an insulation layer with a hole for exposing the electrode; a wiring consisting of a Cr or Ti layer, which is connected to the electrode and closely contacts with the insulation layer, and of a Cu layer which is closely contacts with the Cr or Ti layer; a protective film which covers the wiring and is provided with another hole for soldering; and a solder for the outer connection which is mounted in the both holes and brought to diffuse into the Cu layer to produce an alloy, and brought to reach the Cr or Ti layer thereby connecting the solder to the Cr or Ti layer.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: June 29, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yasumori Narizuka, Mitsuko Itou, Yoshihide Yamaguchi, Hiroyuki Tenmei
  • Patent number: 6624504
    Abstract: A semiconductor apparatus includes a semiconductor device having circuit electrodes aligned centrally of the semiconductor apparatus. A first electrically insulating layer is formed on said semiconductor device with said circuit electrodes being exposed from said first insulating layer. A second electrically insulating layer is formed on said first insulating layer, and external connection terminals are formed on said second insulating layer. A wiring is formed on said second insulating layer to electrically connect said external connect terminals to said circuit electrodes of said semiconductor device, and a third electrically insulating layer is formed on said second insulating layer and on said wiring. Particles are provided in the second insulating layer to control a shape of said second insulating layer.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: September 23, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kosuke Inoue, Hiroyuki Tenmei, Yoshihide Yamaguchi, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Madoka Minagawa, Naoya Kanda, Ichiro Anjo, Asao Nishimura, Akira Yajima, Kenji Ujiie
  • Patent number: 6610934
    Abstract: A multi-chip module including semiconductor devices and a wiring substrate for mounting the semiconductor devices in which the wiring substrate comprises a glass substrate having holes formed by sand blasting and a wiring layer formed on the surface of the glass substrate and having wiring and an insulation layer.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: August 26, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihide Yamaguchi, Takao Terabayashi, Hiroyuki Tenmei, Hiroshi Hozoji, Naoya Kanda
  • Publication number: 20030109079
    Abstract: In the re-wiring formation process of a WLCSP, at least some of the re-wiring lines 3 that connect the bonding pads 1 and bump pads 2 of the semiconductor chips are formed using a photolithographic process that does not use a photomask. In this re-wiring formation process, standard portions are formed by development following photomask exposure, and portions that are to be designed corresponding to customer specifications are subjected to additional development following additional maskless exposure in the final stage.
    Type: Application
    Filed: July 30, 2002
    Publication date: June 12, 2003
    Inventors: Yoshihide Yamaguchi, Hiroyuki Tenmei, Hiroshi Hozoji, Naoya Kanda
  • Publication number: 20030104183
    Abstract: There are provided a high density and low manufacturing cost wiring board with high reliability in connection, a semiconductor device and a producing method therefor. The invention relates to a wiring board comprising a board having an electrode and being coated with an insulation layer with a hole for exposing the electrode; a wiring consisting of a Cr or Ti layer, which is connected to the electrode and closely contacts with the insulation layer, and of a Cu layer which is closely contacts with the Cr or Ti layer; a protective film which covers the wiring and is provided with another hole for soldering; and a solder for the outer connection which is mounted in the both holes and brought to diffuse into the Cu layer to produce an alloy, and brought to reach the Cr or Ti layer thereby connecting the solder to the Cr or Ti layer.
    Type: Application
    Filed: November 21, 2002
    Publication date: June 5, 2003
    Inventors: Yasunori Narizuka, Mitsuko Itou, Yoshihide Yamaguchi, Hiroyuki Tenmei
  • Publication number: 20030071331
    Abstract: A semiconductor device which includes a semiconductor chip, an insulating film formed on the semiconductor chip, a plurality of projected stress relaxation materials formed on the insulating film, projected electrodes covering at least tops of the stress relaxation materials, and wiring lines for electrically connecting the projected electrodes and element electrodes of the semiconductor chip.
    Type: Application
    Filed: October 17, 2002
    Publication date: April 17, 2003
    Inventors: Yoshihide Yamaguchi, Shigeharu Tsunoda, Hiroyuki Tenmei, Hiroshi Hozoji, Naoya Kanda
  • Patent number: 6515372
    Abstract: There are provided a high density and low manufacturing cost wiring board with high reliability in connection, a semiconductor device and a producing method therefor.The invention relates to a wiring board comprising a board having an electrode and being coated with an insulation layer with a hole for exposing the electrode; a wiring consisting of a Cr or Ti layer, which is connected to the electrode and closely contacts with the insulation layer, and of a Cu layer which is closely contacts with the Cr or Ti layer; a protective film which covers the wiring and is provided with another hole for soldering; and a solder for the outer connection which is mounted in the both holes and brought to diffuse into the Cu layer to produce an alloy, and brought to reach the Cr or Ti layer thereby connecting the solder to the Cr or Ti layer.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: February 4, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Yasumori Narizuka, Mitsuko Itou, Yoshihide Yamaguchi, Hiroyuki Tenmei
  • Publication number: 20020180027
    Abstract: A multi-chip module including semiconductor devices and a wiring substrate for mounting the semiconductor devices in which the wiring substrate comprises a glass substrate having holes formed by sand blasting and a wiring layer formed on the surface of the glass substrate and having wiring and an insulation layer.
    Type: Application
    Filed: November 29, 2001
    Publication date: December 5, 2002
    Inventors: Yoshihide Yamaguchi, Takao Terabayashi, Hiroyuki Tenmei, Hiroshi Hozoji, Naoya Kanda
  • Publication number: 20020180015
    Abstract: A multi-chip module including semiconductor devices and a wiring substrate for mounting the semiconductor devices in which the wiring substrate comprises a glass substrate having holes formed by sand blasting and a wiring layer formed on the surface of the glass substrate and having wiring and an insulation layer.
    Type: Application
    Filed: November 30, 2001
    Publication date: December 5, 2002
    Inventors: Yoshihide Yamaguchi, Takao Terabayashi, Hiroyuki Tenmei, Hiroshi Hozoji, Naoya Kanda
  • Publication number: 20020079575
    Abstract: A semiconductor module, comprising a wiring substrate on which wiring is formed, a semiconductor device electrically connected to the wiring formed on the wiring substrate, and an external connection terminal arranged on the semiconductor device mounted side of the wiring substrate so as to be a connected portion between the wiring and the outside electrically connected thereto, wherein there is formed an insulating resin layer thicker than the semiconductor device between the wiring substrate and the external connection terminal.
    Type: Application
    Filed: August 16, 2001
    Publication date: June 27, 2002
    Inventors: Hiroshi Hozoji, Yoshihide Yamaguchi, Naoya Kanda, Shigeharu Tunoda, Hiroyuki Tenmei
  • Publication number: 20020063332
    Abstract: The object of the present invention is to realize a semiconductor device enabling a flip chip connection without use of underfill.
    Type: Application
    Filed: March 20, 2001
    Publication date: May 30, 2002
    Inventors: Yoshihide Yamaguchi, Hiroyuki Tenmei, Kosuke Inoue, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Naoya Kanda, Madoka Minagawa, Ichiro Anjo, Asao Nishimura, Kenji Ujiie, Akira Yajima
  • Publication number: 20020025655
    Abstract: The present invention is a semiconductor device having the semiconductor element 1 obtained by cutting a semiconductor wafer with the electrode pad 2 formed on one side along the scribe line, the semiconductor element protective layer 7 on the semiconductor element 1 which has the opening 7(1) on the pad 2, the stress cushioning layer 3 on the layer 7 which has the opening 3(1) on the pad 2, the lead wire portion 4 reaching the layer 3 from the electrode pad 2 via the openings 7(1) and 3(1), the external electrodes 6 on the lead wire portion 4, and the conductor protective layer 5 on the layer 3 and the layer 7, the layer 3, and the conductor protective layer 5 form the respective end faces on the end surface 1(1) of the semiconductor element 1 inside the scribe line and expose the range from the end face of the end surface 1(1) to the inside of the scribe line.
    Type: Application
    Filed: March 16, 2001
    Publication date: February 28, 2002
    Inventors: Toshiya Satoh, Masahiko Ogino, Tadanori Segawa, Yoshihide Yamaguchi, Hiroyuki Tenmei, Atsushi Kazama, Ichiro Anjo, Asao Nishimura