Patents by Inventor Hiroyuki Utsunomiya
Hiroyuki Utsunomiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220361521Abstract: Provided are an oil or fat based confectionery having the original pleasant flavor of a functional ingredient, and a method for producing the oil or fat based confectionery. The oil or fat based confectionery is an oil or fat based confectionery that includes a functional food containing a functional ingredient having at least one of bitterness and astringency, and an oil or fat having a solid fat content (SFC) of 70% or more at 25° C. and a SFC of less than 15% at 35° C.; has a granularity of 30 ?m or less; has a content of the functional food of 8% by mass or more and 40% by mass or less and a content of sucrose of less than 24% by mass with respect to the oil or fat based confectionery as a whole; and contains no milk ingredient.Type: ApplicationFiled: June 24, 2020Publication date: November 17, 2022Applicant: MEIJI CO., LTD.Inventors: Kazuhiro MUKAIYAMA, Kaoru HIGAKI, Hiroyuki UTSUNOMIYA
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Publication number: 20220346403Abstract: An object of the present invention is to provide a cacao bean-derived food material showing little oil seepage and various foods using the same. A composition having a particle size distribution in the range of 10 ?m to 1.5 mm and containing undisrupted cacao bean cells is provided. A composition containing undisrupted cacao bean cells, which has a free fat content ratio of 60% by weight or lower based on oil content is also provided. A composition containing 30% or more of undisrupted cells in cacao bean cells is further provided. A composition containing undisrupted cacao bean cells, which has a breaking strength of 3 kgf or lower is further provided.Type: ApplicationFiled: October 1, 2020Publication date: November 3, 2022Applicant: MEIJI CO., LTD.Inventors: Koki MATSUDA, Fumito MIYA, Jerchyuan LIN, Kaoru HIGAKI, Hiroyuki UTSUNOMIYA
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Publication number: 20220117253Abstract: A water-containing chocolate-like confectionery, which comprises an oil-in-water type emulsified mixture, wherein the mixture has a water content of 20% by weight or less, and a water activity of 0.7 or less.Type: ApplicationFiled: November 29, 2019Publication date: April 21, 2022Applicant: MEIJI CO., LTD.Inventors: Kazuya INOUE, Masamichi TOKUNAGA, Kaoru HIGAKI, Hiroyuki UTSUNOMIYA
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Patent number: 10840193Abstract: A semiconductor device includes a semiconductor substrate 101 containing a circuit region CR and a chip outer peripheral region PR provided adjacent thereto, a first interlayer-insulating film 102 provided on the semiconductor substrate 101, a second interlayer-insulating film 104 provided on the first interlayer-insulating film 102, a first step ST1 provided between the semiconductor substrate 101 and the first interlayer-insulating film 102 so that the chip outer peripheral region PR side is lower than the circuit region CR side in the chip outer peripheral region PR, and a second step ST2 located on the circuit region CR side relative to the first step ST1 and provided in the second interlayer-insulating film 104 in the chip outer peripheral region PR.Type: GrantFiled: May 31, 2019Date of Patent: November 17, 2020Assignee: ABLIC INC.Inventor: Hiroyuki Utsunomiya
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Patent number: 10636707Abstract: Provided is a method of manufacturing a semiconductor device capable of dividing a wafer with metal formed on a rear surface thereof into individual pieces while suppressing chipping and defective cuts. The method of manufacturing a semiconductor device includes: forming a metal layer on a rear surface of a semiconductor substrate; performing blade dicing for the metal layer; and performing stealth Dicing® for the semiconductor substrate.Type: GrantFiled: September 7, 2018Date of Patent: April 28, 2020Assignee: ABLIC INC.Inventor: Hiroyuki Utsunomiya
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Publication number: 20190371742Abstract: A semiconductor device includes a semiconductor substrate 101 containing a circuit region CR and a chip outer peripheral region PR provided adjacent thereto, a first interlayer-insulating film 102 provided on the semiconductor substrate 101, a second interlayer-insulating film 104 provided on the first interlayer-insulating film 102, a first step ST1 provided between the semiconductor substrate 101 and the first interlayer-insulating film 102 so that the chip outer peripheral region PR side is lower than the circuit region CR side in the chip outer peripheral region PR, and a second step ST2 located on the circuit region CR side relative to the first step ST1 and provided in the second interlayer-insulating film 104 in the chip outer peripheral region PR.Type: ApplicationFiled: May 31, 2019Publication date: December 5, 2019Inventor: Hiroyuki Utsunomiya
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Patent number: 10483223Abstract: A slit is formed along a coupling portion at which a second interconnect is connected to a relatively large area interconnect or pad. Since tensile stress of a resist that is caused due to baking, UV curing, or other treatments in photolithography can be dispersed, contraction and deformation of the resist at an end of the second interconnect can be alleviated, and dimensions and shape of a interconnect, which is formed by etching, can be stabilized.Type: GrantFiled: August 9, 2017Date of Patent: November 19, 2019Assignee: ABLIC INC.Inventor: Hiroyuki Utsunomiya
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Publication number: 20190080964Abstract: Provided is a method of manufacturing a semiconductor device capable of dividing a wafer with metal formed on a rear surface thereof into individual pieces while suppressing chipping and defective cuts. The method of manufacturing a semiconductor device includes: forming a metal layer on a rear surface of a semiconductor substrate; performing blade dicing for the metal layer; and performing stealth dicing® for the semiconductor substrate.Type: ApplicationFiled: September 7, 2018Publication date: March 14, 2019Inventor: Hiroyuki UTSUNOMIYA
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Patent number: 10143216Abstract: The present invention relates to a coated confection in which the wear resistance and shape retention property in high temperature of the center thereof are improved by coating a sufficient amount of shellac on a center with a complex shape. More particularly, the present invention relates to a coated confection composed of a center composed of an oil-based confection and shellac coating the center, wherein a coating rate of shellac is 0.1 to 10%.Type: GrantFiled: October 5, 2012Date of Patent: December 4, 2018Assignee: MEIJI CO., LTD.Inventors: Tadashi Matsuura, Maki Hiraoka, Naoko Takai, Hiroyuki Utsunomiya
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Patent number: 10008466Abstract: A flip-chip mounting technique with high reliability is provided in flip-chip mounting using a Cu pillar. In a semiconductor device to be coupled to a mounting board via a Cu pillar, the Cu pillar is caused to have a laminated structure including a pillar layer, a barrier layer, and a bump in this order from below, and the bump is formed to be smaller than the barrier layer.Type: GrantFiled: October 10, 2017Date of Patent: June 26, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Hiroyuki Utsunomiya
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Publication number: 20180076150Abstract: Provided are a semiconductor chip, a semiconductor apparatus, a semiconductor wafer, and a semiconductor wafer dicing method in which chipping is prevented while securing an effective region of the semiconductor chip to have a sufficient area. Each semiconductor chip region which becomes a semiconductor chip has a rectangular shape, and includes non-effective regions in which no circuit device is placed. The non-effective regions are provided only at two corner portions located at two ends of an arbitrary side of the rectangular shape. The semiconductor wafer has a plurality of semiconductor chip regions arranged so that all non-effective regions face the traveling direction of a dicing blade in a second dicing step.Type: ApplicationFiled: September 5, 2017Publication date: March 15, 2018Inventor: Hiroyuki UTSUNOMIYA
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Publication number: 20180047691Abstract: A flip-chip mounting technique with high reliability is provided in flip-chip mounting using a Cu pillar. In a semiconductor device to be coupled to a mounting board via a Cu pillar, the Cu pillar is caused to have a laminated structure including a pillar layer, a barrier layer, and a bump in this order from below, and the bump is formed to be smaller than the barrier layer.Type: ApplicationFiled: October 10, 2017Publication date: February 15, 2018Inventor: Hiroyuki UTSUNOMIYA
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Publication number: 20180047684Abstract: A slit is formed along a coupling portion at which a second interconnect is connected to a relatively large area interconnect or pad. Since tensile stress of a resist that is caused due to baking, UV curing, or other treatments in photolithography can be dispersed, contraction and deformation of the resist at an end of the second interconnect can be alleviated, and dimensions and shape of a interconnect, which is formed by etching, can be stabilized.Type: ApplicationFiled: August 9, 2017Publication date: February 15, 2018Inventor: Hiroyuki UTSUNOMIYA
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Patent number: 9818709Abstract: A flip-chip mounting technique with high reliability is provided in flip-chip mounting using a Cu pillar. In a semiconductor device to be coupled to a mounting board via a Cu pillar, the Cu pillar is caused to have a laminated structure including a pillar layer, a barrier layer, and a bump in this order from below, and the bump is formed to be smaller than the barrier layer.Type: GrantFiled: April 13, 2016Date of Patent: November 14, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Hiroyuki Utsunomiya
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Publication number: 20170318829Abstract: Disclosed is a chocolate bar containing sucrose palmitate and having a cacao mass content of 35 mass % or more, wherein (i) a sucrose palmitate content is between 0.2 mass % and 0.5 mass % inclusive, and a thickness of the chocolate bar is between 1 mm and 3 mm, inclusive, or (ii) a sucrose palmitate content is between 0.1 mass % and 0.5 mass %, inclusive, and a thickness of the chocolate bar is between 1 mm and 2 mm, inclusive.Type: ApplicationFiled: November 20, 2015Publication date: November 9, 2017Applicant: Meiji Co., Ltd.Inventors: Goro Misaki, Seiichi Fujiwara, Hiroyuki Utsunomiya
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Patent number: 9648893Abstract: Disclosed is an aerated fat-based confectionery that, unlike a conventional shell-type or tapered shape, has a novel shape, that is, a cubic or rectangular parallelepiped shape having top, bottom, and side surfaces in contact with and perpendicularly to each other, or any shape such as an animal or flower shape having a given thickness, has a light texture and a sharp melt-in-the-mouth sensation, does not require alignment in packaging. The confectionery can be obtained by aerating a fat-based confectionery mass having a fat content of 30 to 60% by weight such as chocolate to a specific gravity of 0.5 to 1.0 and cutting the aerated mass with a heated wire so that the side surface is perpendicularly to the top and bottom surfaces.Type: GrantFiled: September 15, 2011Date of Patent: May 16, 2017Assignee: MEIJI CO., LTD.Inventors: Hiroyuki Utsunomiya, Masamitsu Tanaka, Yuka Nagashima, Takanori Chiwata
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Publication number: 20170127697Abstract: There is disclosed a method for manufacturing baked confectionery, comprising: a step of adding water and polyglycerol polyricinoleate to an fat-based confectionery dough; a step of molding the resulting fat-based confectionery dough into a predetermined shape; and a step of baking the molded product. According to this manufacturing method, handleability and workability during molding of the fat-based confectionery dough can be ensured, while improving the shape retention during baking of the fat-based confectionery.Type: ApplicationFiled: July 6, 2015Publication date: May 11, 2017Applicant: Meiji Co., Ltd.Inventors: Noriyuki Hirota, Tadashi Matsuura, Hiroyuki Utsunomiya
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Publication number: 20160322322Abstract: A flip-chip mounting technique with high reliability is provided in flip-chip mounting using a Cu pillar. In a semiconductor device to be coupled to a mounting board via a Cu pillar, the Cu pillar is caused to have a laminated structure including a pillar layer, a barrier layer, and a bump in this order from below, and the bump is formed to be smaller than the barrier layer.Type: ApplicationFiled: April 13, 2016Publication date: November 3, 2016Inventor: Hiroyuki UTSUNOMIYA
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Publication number: 20150004299Abstract: Described herein is a baked confectionery which is produced by baking a fat-based confectionery comprising a nut, wherein the baked confectionery preferably comprises a compound selected from the group consisting of isomaltulose, mannitol, and maltitol. Also, described herein is a method for producing a baked confectionery, comprising preparing a fat-based confectionery comprising nuts and preferably also comprising a compound selected from the group consisting of isomaltulose, mannitol, and maltitol, and baking the fat-based confectionery.Type: ApplicationFiled: February 27, 2013Publication date: January 1, 2015Applicant: MEIJI CO., LTD.Inventors: Takashi Katagiri, Goro Misaki, Saori Toriwa, Hiroyuki Utsunomiya
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Publication number: 20140234492Abstract: The present invention relates to a coated confection in which the wear resistance and shape retention property in high temperature of the center thereof are improved by coating a sufficient amount of shellac on a center with a complex shape. More particularly, the present invention relates to a coated confection composed of a center composed of an oil-based confection and shellac coating the center, wherein a coating rate of shellac is 0.1 to 10%.Type: ApplicationFiled: October 5, 2012Publication date: August 21, 2014Applicant: MEIJI CO., LTD.Inventors: Tadashi Matsuura, Maki Hiraoka, Naoko Takai, Hiroyuki Utsunomiya