Patents by Inventor Hiroyuki Yamagishi

Hiroyuki Yamagishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7006017
    Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. For example, code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0” while two's complement q1 of a sum of code sequences c1 up to that time is “1”.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: February 28, 2006
    Assignee: Sony Corporation
    Inventors: Makoto Noda, Hiroyuki Yamagishi
  • Patent number: 6989774
    Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. For example, code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0” while two's complement q1 of a sum of code sequences c1 up to that time is “1”.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: January 24, 2006
    Assignee: Sony Corporation
    Inventors: Makoto Noda, Hiroyuki Yamagishi
  • Patent number: 6989775
    Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. For example, code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0” while two's complement q1 of a sum of code sequences c1 up to that time is “1”.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: January 24, 2006
    Assignee: Sony Corporation
    Inventors: Makoto Noda, Hiroyuki Yamagishi
  • Publication number: 20050204272
    Abstract: In implementing calculations in a log area of a message passing algorithm, the results of calculations of a message from a check node to a variable node are to be found readily on a circuit or by a computer. To this end, a decoding apparatus, decoding the LDPC code using the message passing algorithm, sets a message as a log likelihood ratio having, as a base, a real number “a” which is a power of 2, and includes a check node processing calculating unit for receiving a message Qm,n from a bit node to calculate a message Rm,n from a check node.
    Type: Application
    Filed: January 31, 2005
    Publication date: September 15, 2005
    Inventor: Hiroyuki Yamagishi
  • Publication number: 20050174264
    Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. For example, code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0” while two's complement q1 of a sum of code sequences c1 up to that time is “1”.
    Type: Application
    Filed: March 31, 2005
    Publication date: August 11, 2005
    Inventors: Makoto Noda, Hiroyuki Yamagishi
  • Patent number: 6928602
    Abstract: An encoding method for encoding information bits into a codeword by a linear code is provided. The information bits appear in the codeword as a part of the codeword. The linear code is a code in which a codeword resulting from cyclically shifting an arbitrary codeword by p bit positions is also a codeword. A code polynomial having the codeword in which the information bits appear as a part thereof is computed by executing an arithmetic operation of p polynomials G0(x), . . . , Gp?1(x) and a polynomial having the information bits as coefficients. Accordingly, a quasi-cyclic (QC) code can be encoded by only polynomial operations, and an encoder can be simplified.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: August 9, 2005
    Assignee: Sony Corporation
    Inventors: Hiroyuki Yamagishi, Yoshihide Shimpuku
  • Publication number: 20050168357
    Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. For example, code states s0 and s1 when information sequences do and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences co up to a time when the code states are equal to each other is “0” while two's complement q1 of a sum of code sequences c1 up to that time is “1”.
    Type: Application
    Filed: March 31, 2005
    Publication date: August 4, 2005
    Inventors: Makoto Noda, Hiroyuki Yamagishi
  • Publication number: 20050168359
    Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. For example, code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0” while two's complement q1 of a sum of code sequences c1 up to that time is “1”.
    Type: Application
    Filed: March 31, 2005
    Publication date: August 4, 2005
    Inventors: Makoto Noda, Hiroyuki Yamagishi
  • Publication number: 20050168356
    Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. For example, code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0” while two's complement q1 of a sum of code sequences c1 up to that time is “1”.
    Type: Application
    Filed: March 31, 2005
    Publication date: August 4, 2005
    Inventors: Makoto Noda, Hiroyuki Yamagishi
  • Patent number: 6891483
    Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. Code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0” while two's complement q1 of a sum of code sequences c1 up to that time is “1”. That is, the condition that q0?q1 is met.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: May 10, 2005
    Assignee: Sony Corporation
    Inventors: Makoto Noda, Hiroyuki Yamagishi
  • Publication number: 20040217888
    Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0≠q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word.
    Type: Application
    Filed: March 10, 2004
    Publication date: November 4, 2004
    Inventors: Makoto Noda, Hiroyuki Yamagishi
  • Publication number: 20040205446
    Abstract: The states S0 to S9 in a state-transition table, which is a combination of (d,k) Run Length Limited (RLL) codes and a Parallel Response (PR1) channel having a precoder, correspond to ten states defined by dividing each of the five states S0 to S4 in the state-transition table used to encode data into (d,k) RLL codes. That is, the states S0 to S4 correspond to the cases where the immediately preceding Non Return to Zero (NRZ) code is “0” in the state-transition table of the (d,k) RLL codes, and the states S5 to S9 correspond to the cases where the immediately preceding NRZ code is “1” in the state-transition table of the (d,k) RLL codes. This method can be applied to recording/reproducing apparatuses.
    Type: Application
    Filed: February 17, 2004
    Publication date: October 14, 2004
    Inventor: Hiroyuki Yamagishi
  • Publication number: 20030079172
    Abstract: An encoding method for encoding information bits into a codeword by a linear code is provided. The information bits appear in the codeword as a part of the codeword. The linear code is a code in which a codeword resulting from cyclically shifting an arbitrary codeword by p bit positions is also a codeword. A code polynomial having the codeword in which the information bits appear as a part thereof is computed by executing an arithmetic operation of p polynomials G0(x), . . . , Gp−1(x) and a polynomial having the information bits as coefficients. Accordingly, a quasi-cyclic (QC) code can be encoded by only polynomial operations, and an encoder can be simplified.
    Type: Application
    Filed: July 16, 2002
    Publication date: April 24, 2003
    Inventors: Hiroyuki Yamagishi, Yoshihide Shimpuku