Patents by Inventor Hiroyuki Yoda

Hiroyuki Yoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110101601
    Abstract: Provided is a stacking mechanism that includes a paper feed tray including a paper inlet through which a recording medium to undergo a recording process is to be supplied; a paper output tray on which the recording medium that has undergone the recording process and been transported is to be stacked, the paper output tray being superposed on the paper feed tray; a pivotal shaft that allows the paper output tray to pivot with respect to the paper feed tray so as to expose the paper inlet of the paper feed tray; and a lock mechanism that locks the paper output tray displaced about the pivotal shaft, at a predetermined position.
    Type: Application
    Filed: October 28, 2010
    Publication date: May 5, 2011
    Applicant: Seiko Epson Corporation
    Inventors: Hiroyuki YODA, Shigeto OMATSU
  • Publication number: 20100081269
    Abstract: A method for manufacturing semiconductor device which includes forming a first metal film over an electrode pad disposed on a substrate, forming a second metal film on the first metal film, forming a first oxide film on a surface of the first metal film and a second oxide film on a surface of the second metal film by oxidizing the surfaces of the first metal film and the second metal film, removing the first oxide film, and melting the second metal film after removing the first oxide film.
    Type: Application
    Filed: September 30, 2009
    Publication date: April 1, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Yutaka Makino, Masamitsu Ikumo, Hiroyuki Yoda
  • Publication number: 20080293234
    Abstract: A semiconductor device includes a plurality of electrode layers provided at designated positions of a semiconductor substrate, an organic insulation film formed on the semiconductor substrate by selectively exposing designated areas of the electrode layers, and projection electrodes for outside connection, the projection electrodes being formed on the designated areas of the electrode layers. Thickness of the organic insulation film situated in the vicinity of the periphery of the projection electrodes is greater than thickness of the organic insulation film situated between the projection electrodes.
    Type: Application
    Filed: June 25, 2008
    Publication date: November 27, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Masamitsu Ikumo, Hiroyuki Yoda, Eiji Watanabe
  • Patent number: 7417326
    Abstract: A semiconductor device includes a plurality of electrode layers provided at designated positions of a semiconductor substrate, an organic insulation film formed on the semiconductor substrate by selectively exposing designated areas of the electrode layers, and projection electrodes for outside connection, the projection electrodes being formed on the designated areas of the electrode layers. Thickness of the organic insulation film situated in the vicinity of the periphery of the projection electrodes is greater than thickness of the organic insulation film situated between the projection electrodes.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: August 26, 2008
    Assignee: Fujitsu Limited
    Inventors: Masamitsu Ikumo, Hiroyuki Yoda, Eiji Watanabe
  • Patent number: 7276386
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming barrier metals on first electrodes provided on a chip of the semiconductor device, implementing a predetermined test on the semiconductor device by applying a signal to the semiconductor device via at least one of the barrier metals, and forming second protruded electrodes on the barrier metals. The predetermined tests are implemented before forming second protruded electrodes on the barrier metals.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: October 2, 2007
    Assignee: Fujitsu Limited
    Inventors: Katsumi Miyata, Eiji Watanabe, Hiroyuki Yoda
  • Publication number: 20070138635
    Abstract: A semiconductor device includes a plurality of electrode layers provided at designated positions of a semiconductor substrate, an organic insulation film formed on the semiconductor substrate by selectively exposing designated areas of the electrode layers, and projection electrodes for outside connection, the projection electrodes being formed on the designated areas of the electrode layers. Thickness of the organic insulation film situated in the vicinity of the periphery of the projection electrodes is greater than thickness of the organic insulation film situated between the projection electrodes.
    Type: Application
    Filed: March 14, 2006
    Publication date: June 21, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Masamitsu Ikumo, Hiroyuki Yoda, Eiji Watanabe
  • Patent number: 7202410
    Abstract: Between a light receiving glass and a backside glass a plurality of solar battery cells form a matrix of solar battery cells and a translucent, intermediate layer of film is also interposed to configure a photovoltaic module having a light receptive, glass laminate structure, wherein at least one of a back surface of the solar battery cell and a front surface of the backside glass observed indoors has a film stuck thereon. For a photovoltaic module having a light receptive, multi-layer structure, a glass observed indoors also has a film stuck thereon. The solar battery cell can thus have a back surface with a lead frame, a mark of paste applied for collection of electricity covered with the film to provide an improved, externally observed design and an increased product value.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: April 10, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akimasa Umemoto, Hiroyuki Yoda, Noriaki Shibuya
  • Publication number: 20060258045
    Abstract: A semiconductor device includes a semiconductor substrate and an array of protruding electrodes arranged at a pitch X1. Each of the protruding electrodes has a height X3 and is formed on a barrier metal base of diameter X2 coupled to an electrode arranged on the semiconductor substrate so as to satisfy the relations (X½)?X2?(3*X¼) and (X½)?X3?(3*X¼).
    Type: Application
    Filed: April 27, 2006
    Publication date: November 16, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Masahiko Ishiguri, Hirohisa Matsuki, Hiroyuki Yoda, Tadahiro Okamoto, Masamitsu Ikumo, Shuichi Chiba
  • Patent number: 7064436
    Abstract: A semiconductor device includes a semiconductor substrate and an array of protruding electrodes arranged at a pitch X1. Each of the protruding electrodes has a height X3 and is formed on a barrier metal base of diameter X2 coupled to an electrode arranged on the semiconductor substrate so as to satisfy the relations (X1/2)?X2?(3*X1/4) and (X1/2)?X3?(3*X1/4).
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: June 20, 2006
    Assignee: Fujitsu Limited
    Inventors: Masahiko Ishiguri, Hirohisa Matsuki, Hiroyuki Yoda, Tadahiro Okamoto, Masamitsu Ikumo, Shuichi Chiba
  • Publication number: 20050140004
    Abstract: A semiconductor device includes a semiconductor substrate and an array of protruding electrodes arranged at a pitch X1. Each of the protruding electrodes has a height X3 and is formed on a barrier metal base of diameter X2 coupled to an electrode arranged on the semiconductor substrate so as to satisfy the relations (X1/2)?X2?(3*X1/4) and (X1/2)?X3?(3*X1/4).
    Type: Application
    Filed: November 23, 2004
    Publication date: June 30, 2005
    Inventors: Masahiko Ishiguri, Hirohisa Matsuki, Hiroyuki Yoda, Tadahiro Okamoto, Masamitsu Ikumo, Shuichi Chiba
  • Publication number: 20050006792
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming barrier metals on first electrodes provided on a chip of the semiconductor device, implementing a predetermined test on the semiconductor device by applying a signal to the semiconductor device via at least one of the barrier metals, and forming second protruded electrodes on the barrier metals. The predetermined tests are implemented before forming second protruded electrodes on the barrier metals.
    Type: Application
    Filed: August 10, 2004
    Publication date: January 13, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Katsumi Miyata, Eiji Watanabe, Hiroyuki Yoda
  • Publication number: 20040182432
    Abstract: A photovoltaic module with sealed insulating glass includes opposite, front and rear plates of glass, a frame forming a space therebetween, and a photovoltaic module subassembly arranged in the space. The subassembly includes a plurality of photovoltaic cells, a first, translucent plate member of resin located adjacent to a light receiving surface of the cell, a second, translucent plate member of resin located adjacent to a non-light receiving surface of the cell, and a translucent filler layer located between the plate members of resin to seal the photovoltaic cells. Thus the photovoltaic module with sealed insulating glass can be reusable and excellent in sound and heat insulation, and also miniaturized and significantly strong and highly antiweatherable.
    Type: Application
    Filed: February 19, 2004
    Publication date: September 23, 2004
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Hiroyuki Yoda, Kousuke Ueda
  • Patent number: 6528718
    Abstract: A solar battery module in use has a solar battery panel and a frame body. The solar battery panel is constituted by laminating a front cover, a filler, a crystal solar battery cell, another filler, and a back cover on one another in this order. The frame body surrounds the outer periphery of the solar battery. At each corner of one side of the frame body is formed a notch with its open end facing toward the light-receiving surface. Under rainfall, rainwater which fell down onto the light-receiving surface flows toward below the solar battery module, and is then held back by the frame member provided on the frame body. The rainwater remaining flows into the notch. In the notch, the rainwater is guided toward above the frame member on the principles of siphon action so as to be discharged out of the solar battery module.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: March 4, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroyuki Yoda, Akimasa Umemoto
  • Publication number: 20030010378
    Abstract: Two sheet glasses are superposed at a prescribed distance with a spacer interposed. By these two sheet glasses and a spacer, a double glazing glass having a sealed inner space is formed. In the inner space of the double glazing glass, a plurality of solar cells that have been subjected to weather resistant sealing process are provided. As a result, a double glazing glass type solar cell module is obtained, which is lightweight, of which manufacturing process is simple and which has high reliability over a long period of time.
    Type: Application
    Filed: July 10, 2002
    Publication date: January 16, 2003
    Inventors: Hiroyuki Yoda, Akimasa Umemoto
  • Publication number: 20020153038
    Abstract: Between a light receiving glass and a backside glass a plurality of solar battery cells form a matrix of solar battery cells and a translucent, intermediate layer of film is also interposed to configure a photovoltaic module having a light receptive, glass laminate structure, wherein at least one of a back surface of the solar battery cell and a front surface of the backside glass observed indoors has a film stuck thereon. For a photovoltaic module having a light receptive, multi-layer structure, a glass observed indoors also has a film stuck thereon. The solar battery cell can thus have a back surface with a lead frame, a mark of paste applied for collection of electricity covered with the film to provide an improved, externally observed design and an increased product value.
    Type: Application
    Filed: April 22, 2002
    Publication date: October 24, 2002
    Inventors: Akimasa Umemoto, Hiroyuki Yoda, Noriaki Shibuya
  • Publication number: 20020102832
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming barrier metals on first electrodes provided on a chip of the semiconductor device, implementing a predetermined test on the semiconductor device by applying a signal to the semiconductor device via at least one of the barrier metals, and forming second protruded electrodes on the barrier metals. The predetermined tests are implemented before forming second protruded electrodes on the barrier metals.
    Type: Application
    Filed: January 6, 2000
    Publication date: August 1, 2002
    Inventors: KATSUMI MIYATA, EIJI WATANABE, HIROYUKI YODA
  • Publication number: 20020029799
    Abstract: A solar battery module in use has a solar battery panel and a frame body. The solar battery panel is constituted by laminating a front cover, a filler, a crystal solar battery cell, another filler, and a back cover on one another in this order. The frame body surrounds the outer periphery of the solar battery. At each corner of one side of the frame body is formed a notch with its open end facing toward the light-receiving surface. Under rainfall, rainwater which fell down onto the light-receiving surface flows toward below the solar battery module, and is then held back by the frame member provided on the frame body. The rainwater remaining flows into the notch. In the notch, the rainwater is guided toward above the frame member on the principles of siphon action so as to be discharged out of the solar battery module.
    Type: Application
    Filed: September 12, 2001
    Publication date: March 14, 2002
    Inventors: Hiroyuki Yoda, Akimasa Umemoto
  • Patent number: 6218281
    Abstract: A semiconductor substrate is prepared which has a principal surface, an exposed pad made of conductive material being formed in a partial area of the principal surface, and the other area of the principal surface being covered with a first insulating film. A base conductive film is formed on the first insulating film and the pad. A photoresist film having a thickness of 50 &mgr;m or thicker is formed on the base conductive film. An opening is formed through the photoresist film in an area corresponding to the pad to expose a partial surface area of the base conductive film. A conductive bump electrode is deposited on the base conductive film exposed on a bottom of the opening. The photoresist film is removed. This method is suitable for making a fine pitch between bump electrodes.
    Type: Grant
    Filed: November 16, 1998
    Date of Patent: April 17, 2001
    Assignee: Fujitsu Limited
    Inventors: Eiji Watanabe, Hirohisa Matsuki, Kenichi Kado, Kenichi Nagashige, Masanori Onodera, Kunio Kodama, Hiroyuki Yoda, Joji Fujimori, Minoru Nakada, Yutaka Makino
  • Patent number: D523069
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: June 13, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Manabu Akahane, Makoto Kobayashi, Hiroyuki Yoda, Takayuki Iijima
  • Patent number: D539337
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: March 27, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Hideki Kato, Hiroto Miyauchi, Masahiko Kobayashi, Hiroyuki Yoda