Abstract: A semiconductor memory device, including: a cell array block including a plurality of memory cells arranged therein; and a controller, wherein the controller controls the semiconductor memory device so that: an operation of reading out data from a second region in the cell array block is initiated before completion of an operation of outputting data read out from a first region in the cell array block; and the data read out from the second region is output successively after the completion of the operation of outputting data read out from the first region.

Abstract: A semiconductor memory device, including: a cell array block including a plurality of memory cells arranged therein; and a controller, wherein the controller controls the semiconductor memory device so that: an operation of reading out data from a second region in the cell array block is initiated before completion of an operation of outputting data read out from a first region in the cell array block; and the data read out from the second region is output successively after the completion of the operation of outputting data read out from the first region.

Abstract: In a system of using a plurality of memories with a plurality of CPUs, a plurality of memory arrays are placed on the same memory chip with each memory array being individually provided with a data-related circuit, an address-related circuit and a control-related circuit. These memory arrays however share a data terminal, an address terminal and a control terminal for chip external connection. A data, address and control signals are distributed to the memory arrays via three MUX of signal selection circuits controlled with an array selection signal (clock). A signal is supplied to one memory array at rising timing of the clock while a signal is supplied to another memory array at falling timing of the clock. Thus, in memory integration of placing a plurality of memory arrays on one chip, independent operation for each memory array is attained, and no bus arbitration between CPUs is necessary.

Abstract: A non-volatile storage device comprises a non-volatile memory into which data is written per unit area, and a memory controller for controlling writing of data into the non-volatile memory. The memory controller comprises a first storage section for holding data input from the outside of the device, a first control section for writing data which is held by the first storage section and whose amount corresponds to the unit area, into the non-volatile memory in a unit area-by-unit area basis, and writing data which is held by the first storage section and whose amount is less than the unit area, into a second storage section, and a second control section for writing data held by the second storage section into the non-volatile memory.

Abstract: In a system of using a plurality of memories with a plurality of CPUs, a plurality of memory arrays are placed on the same memory chip with each memory array being individually provided with a data-related circuit, an address-related circuit and a control-related circuit. These memory arrays however share a data terminal, an address terminal and a control terminal for chip external connection. A data, address and control signals are distributed to the memory arrays via three MUX of signal selection circuits controlled with an array selection signal (clock). A signal is supplied to one memory array at rising timing of the clock while a signal is supplied to another memory array at falling timing of the clock. Thus, in memory integration of placing a plurality of memory arrays on one chip, independent operation for each memory array is attained, and no bus arbitration between CPUs is necessary.

Abstract: A first semiconductor chip 102 includes an integrated circuit formed on a face which is shown upwards in FIG. 2. A second semiconductor chip 103 includes an integrated circuit formed on a face which is shown downwards in FIG. 2. Between the first semiconductor chip 102 and the second semiconductor chip 103, a non-conductive die pad 107 is interposed. The die pad 107 is provided with connection members 110 protruding from the first semiconductor chip 102 and the second semiconductor chip 103. The connection members 110 are plated on their surfaces so as to be electrically conductive. The integrated circuit on the first semiconductor chip 102 and the integrated circuit on the second semiconductor chip 103 are interconnected by two inter-chip connection wires 104a and 104b, via the connection members 110.

Abstract: A semiconductor apparatus includes serially-connected bodies composed of a switch element and a resistance element respectively interposed between terminals adjacent to one another, conduction-test terminals connected to one and another ends of a series of the serially-connected bodies, and a switch control terminal for collectively controlling all the plural switch elements. Also included are switch elements interposed alternately on the first semiconductor chip side and the second semiconductor chip side between wires adjacent to one another, conduction-test terminals connected to one and another ends of a series of the serially-connected switch elements, and a switch control terminal for collectively controlling all the plural switch elements.

Abstract: The SIP structure package includes a first chip though which signal transmission/reception is performed between the inside and the outside of the package, and a second chip connected to the first chip within the package. The first chip includes interface circuits 6A and 6B for supplying a signal to all the signal terminals of the second chip. The operation of the interface circuits is controlled to be stoppable by a control signal.

Abstract: A first inventive semiconductor device includes: a die pad 1; a mother chip 2; a daughter chip 3; a conductor film 7 formed on the back surface of the daughter chip 3; bumps 4; a lead 5; and a bonding wire 6, as shown in FIG. 1B. The conductor film 7 is connected to an external member via the bonding wire 6 and the lead 5, thus stabilizing a substrate potential. In addition, the conductor film 7 has a high heat conductivity and a low electrical resistance, thereby improving the heat radiation performance of the semiconductor device and suppressing noise radiation.

Abstract: A first semiconductor chip 102 includes an integrated circuit formed on a face which is shown upwards in FIG. 2. A second semiconductor chip 103 includes an integrated circuit formed on a face which is shown downwards in FIG. 2. Between the first semiconductor chip 102 and the second semiconductor chip 103, a non-conductive die pad 107 is interposed. The die pad 107 is provided with connection members 110 protruding from the first semiconductor chip 102 and the second semiconductor chip 103. The connection members 110 are plated on their surfaces so as to be electrically conductive. The integrated circuit on the first semiconductor chip 102 and the integrated circuit on the second semiconductor chip 103 are interconnected by two inter-chip connection wires 104a and 104b, via the connection members 110.

Abstract: A semiconductor apparatus comprises serially-connected bodies comprised of a switch element and a resistance element respectively interposed between terminals adjacent to one another, conduction-test terminals connected to one and another ends of a series of the serially-connected bodies, and a switch control terminal for collectively controlling all the plural switch elements. Also comprised are switch elements interposed alternately on the first semiconductor chip side and the second semiconductor chip side between wires adjacent to one another, conduction-test terminals connected to one and another ends of a series of the serially-connected switch elements, and a switch control terminal for collectively controlling all the plural switch elements.

Abstract: A nonvolatile semiconductor memory device with high repair efficiency prevents over-erasing even if a memory cell is replaced in the word line direction. The nonvolatile semiconductor memory device includes the following: erasing bias circuits for erasing data in normal memory cell arrays and a redundancy memory cell array; erasing decode circuits for decoding defective address information; and redundancy control circuits connected in series so that a preceding stage controls the next in order to store defective address information based on an erasing decode signal and to switch the erasing bias circuits based on the defective address information.

Abstract: A nonvolatile semiconductor memory device with high repair efficiency prevents over-erasing even if a memory cell is replaced in the word line direction. The nonvolatile semiconductor memory device includes the following: erasing bias circuits for erasing data in normal memory cell arrays and a redundancy memory cell array; erasing decode circuits for decoding defective address information; and redundancy control circuits connected in series so that a preceding stage controls the next in order to store defective address information based on an erasing decode signal and to switch the erasing bias circuits based on the defective address information.

Abstract: A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.

Abstract: A driver circuit which drives a signal line includes a first output section for outputting a reference voltage potential to the signal line during a first period and a second output section for outputting one of a first information voltage potential and a second information voltage potential in accordance with an input signal during a second period.

Abstract: A CPU acting as a mother chip, in combination with a DRAM acting as a subsidiary chip, is mounted. A mode output circuit is able to set the storage capacity of the DRAM as well as the refresh cycle of the DRAM for forwarding to a mode input circuit of the CPU through a mode output terminal of the DRAM and a mode input terminal of the CPU. The CPU controls an address generator according to the data from the mode input circuit, to set the number of bits of address data for access to the DRAM according to the DRAM storage capacity and the DRAM refresh cycle.

Abstract: An apparatus for selecting redundant memory cells in integrated circuit memory devices. The apparatus includes eight memory cell blocks, each of which includes a plurality of memory cell groups, a redundant memory cell group of a first set and a redundant memory cell group of a second set; and eight selecting fuse circuit blocks. Four of the selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the first set of any of the eight memory cell blocks, and the other four selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the second set of any of the eight memory cell blocks.

Abstract: A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.

Abstract: A semiconductor memory device according to the present invention includes a plurality of blocks. A plurality of first selection signals, second selection signals, and third selection signals are provided to the blocks.

Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.