Patents by Inventor Hisaki Watanabe

Hisaki Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11772150
    Abstract: A breathable salt core is provided that is placed in a cavity of a casting mold in order to mold a hollow part of a cast product and that is dissolved and removed after casting, the breathable salt core being formed by powder molding innumerable salt particles into a predetermined shape corresponding to the hollow part, wherein a gap that can retain a gas remaining in the cavity in a casting process is formed between the innumerable salt particles that have been powder molded. The breathable salt core thus manufactured assures that residual gas within the cavity pushed by the molten metal to enter the gap formed between salt particles of the salt core, thereby avoiding any incomplete filling of the molten metal, and which can be formed with a simple production process at a low cost.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: October 3, 2023
    Assignee: Honda Foundry Co., Ltd.
    Inventors: Masao Takahashi, Hisaki Watanabe, Kenta Abe, Yohei Sekiguchi
  • Publication number: 20220362837
    Abstract: A breathable salt core is provided that is placed in a cavity of a casting mold in order to mold a hollow part of a cast product and that is dissolved and removed after casting, the breathable salt core being formed by powder molding innumerable salt particles into a predetermined shape corresponding to the hollow part, wherein a gap that can retain a gas remaining in the cavity in a casting process is formed between the innumerable salt particles that have been powder molded. The breathable salt core thus manufactured assures that residual gas within the cavity pushed by the molten metal to enter the gap formed between salt particles of the salt core, thereby avoiding any incomplete filling of the molten metal, and which can be formed with a simple production process at a low cost.
    Type: Application
    Filed: December 20, 2019
    Publication date: November 17, 2022
    Inventors: Masao TAKAHASHI, Hisaki WATANABE, Kenta ABE, Yohei SEKIGUCHI
  • Patent number: 7423472
    Abstract: There is provided a power switching circuit capable of completely breaking a current in an OFF state of a switch connecting power sources even when a voltage difference is generated between the power sources of a plurality of functional blocks separated from each other on an LSI chip. A gate control circuit 1a has a control signal terminal INCNT, a first power imputer terminal IG11, and a second power supply terminal IG12 as input terminals and has a first output terminal OG11 and a second output terminal OG12 as output terminals. The gate of a second P-type transistor P2 is connected to the first output terminal OG11 of the gate control circuit 1a and the gate of a second P-type transistor P2 is connected to the second output terminal OG12 of the gate control circuit 1a, wherein the first P-type transistor P1 and the second P-type transistor P2 are connected in series between a first power source VDD1 and a second power source VDD2 to form a switch section.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: September 9, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaya Hirose, Kinya Daio, Masahiro Gion, Masato Maede, Hisaki Watanabe
  • Publication number: 20060214722
    Abstract: There is provided a power switching circuit capable of completely breaking a current in an OFF state of a switch connecting power sources even when a voltage difference is generated between the power sources of a plurality of functional blocks separated from each other on an LSI chip. A gate control circuit 1a has a control signal terminal INCNT, a first power imputer terminal IG11, and a second power supply terminal IG12 as input terminals and has a first output terminal OG11 and a second output terminal OG12 as output terminals. The gate of a second P-type transistor P2 is connected to the first output terminal OG11 of the gate control circuit 1a and the gate of a second P-type transistor P2 is connected to the second output terminal OG12 of the gate control circuit 1a, wherein the first P-type transistor P1 and the second P-type transistor P2 are connected in series between a first power source VDD1 and a second power source VDD2 to form a switch section.
    Type: Application
    Filed: March 28, 2006
    Publication date: September 28, 2006
    Inventors: Masaya Hirose, Kinya Daio, Masahiro Gion, Masato Maede, Hisaki Watanabe
  • Patent number: 6800883
    Abstract: In a CMOS basic cell used in fabrication of a gate array semiconductor integrated circuit, each of the gate and the diffusion region of a P-channel transistor is in a hooked shape having bent parts respectively bending to the left and right at the upper and lower portions thereof. Similarly, each of the gate and the diffusion region of an N-channel transistor is in a hooked shape having bent parts respectively bending to the left and right at the upper and lower portions thereof. In the case where a semiconductor integrated circuit is fabricated by arranging basic cells having the same structure on the right and left hand sides of this basic cell, the basic cells adjacent to each other are overlapped by portions thereof corresponding to one grid, so that the portions in the hooked shapes can be alternately inlaid with each other. Accordingly, the semiconductor integrated circuit attains a smaller layout area.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: October 5, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeki Furuya, Hisaki Watanabe, Atsushi Mototani
  • Publication number: 20020034110
    Abstract: In a CMOS basic cell used in fabrication of a gate array semiconductor integrated circuit, each of the gate and the diffusion region of a P-channel transistor is in a hooked shape having bent parts respectively bending to the left and right at the upper and lower portions thereof. Similarly, each of the gate and the diffusion region of an N-channel transistor is in a hooked shape having bent parts respectively bending to the left and right at the upper and lower portions thereof. In the case where a semiconductor integrated circuit is fabricated by arranging basic cells having the same structure on the right and left hand sides of this basic cell, the basic cells adjacent to each other are overlapped by portions thereof corresponding to one grid, so that the portions in the hooked shapes can be alternately inlaid with each other. Accordingly, the semiconductor integrated circuit attains a smaller layout area.
    Type: Application
    Filed: August 7, 2001
    Publication date: March 21, 2002
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Shigeki Furuya, Hisaki Watanabe, Atsushi Mototani