Abstract: A semiconductor memory device having a flash write function includes a row decoder (2) decoding external row address for selecting one row of a memory cell array (1'), and circuitry (4, 8) responsive to a flash write designating signal for writing the same data simultaneously to the memory cells connected to the selected row. The semiconductor memory device has at least one memory block (MB1, MB2, MB, MB4), with each of the block having a plurality of column groups (B1, B2, B3, B4) each including a plurality of columns. The memory cell block has a plurality of memory cells arranged in rows and columns which can be accessed at random sequence. The memory device further includes circuitry (6) for generating the mask position designating signal at the time of flash writing, and circuitry (4-1 to 4-n, 7) for prohibiting writing of data to the column group designated by the mask position designating signal.

Abstract: A dual-port memory includes a memory array comprising a plurality of memory elements one of which is accessed at random by a row and column address input so as to enable writing in or reading out of data; at least two serial access memories capable of receiving parallel input of all or a portion of the data of a selected row or column of said memory array; and a switching circuit for switching the respective serial access memories to be in operational states of receiving parallel inputs independently or to be in operational states of outputting their serial outputs successively.

Abstract: Portions adjacent to the tips of a plurality of leads taken out from at least one side of a package for protecting a semiconductor device are embedded in an integral insulating mold resin to maintain intervals between the adjacent leads and, each of the leads is bent at two portions so that the tip portion of each lead is positioned at the lower surface of said package.

Abstract: A microprocessor includes an internal data memory, made up of a plurality of memory cells, each of which includes first and second inverter circuits. In selected memory cells, the logic state of the cell is predetermined upon initiation of the power supply by arranging the inverters of each cell such that they have different transistor ratios. The difference in ratio may be effected by altering the channel width or length of one of the constituent transistors of the respective inverter circuit.