Abstract: A spacer is fixed while an effect on a surface of an active matrix substrate is prevented. An active matrix substrate (1) includes a thin film transistor (11) which is provided on a substrate (2) and which has a recess made at a surface of the thin film transistor, and a spacer (13) fitted in the recess.

Abstract: An active matrix substrate includes a first TFT (10), a second TFT (20) disposed per pixel, and a circuit including the first TFT. The first and second TFTs each include a gate electrode (102A, 102B), a gate insulating layer (103), an oxide semiconductor layer (104A, 104B), and source and drain electrodes in contact with an upper surface of the oxide semiconductor layer. The oxide semiconductor layer (104A, 104B) has a stacked structure including a first semiconductor layer (104e, 104c) in contact with the source and drain electrodes and a second semiconductor layer that is disposed on a substrate-side of the first semiconductor layer and that has a smaller energy gap than the first semiconductor layer. The oxide semiconductor layers (104A) and (104B) are different from each other in terms of the composition and/or the number of stacked layers. The first TFT has a larger threshold voltage than the second TFT.

Abstract: A semiconductor film 21 is provided so as to overlap with a light-shielding film 11 when viewed in a plan view. A second insulating film 30 has a contact hole CH1 that reaches a source electrode 22 and a drain electrode 23. A gate electrode 41 is provided on the second insulating film 30 so as to overlap with the semiconductor film 21 when viewed in a plan view, and at the same time, so as to overlap with none of the source electrode 22 and the drain electrode 23 when viewed in a plan view. A third insulating film 50 is provided on the second insulating film 30 so as to cover the gate electrode 41, and at the same time, so as to be in contact with the source electrode 22 and the drain electrode 23 through the contact hole CH1.

Abstract: A semiconductor device (100) is provided with a thin film transistor including an oxide semiconductor layer (5), a gate electrode (3), a gate insulating layer (4), and a source electrode (7s) and a drain electrode (7d) that are in contact with the oxide semiconductor layer, at least one electrode of the source electrode (7s), the drain electrode (7d), and the gate electrode (3) has a multilayer structure that includes a first layer (3A, 7A) containing copper and a second layer (3B, 7B) containing titanium or molybdenum, the thickness of the first layer (3A, 7A) is more than the thickness of the second layer (3B, 7B), when the source electrode (7s) or the drain electrode (7d) has the multilayer structure, the second layer is arranged on the oxide semiconductor layer side of the first layer so as to be in contact with the surface of the oxide semiconductor layer (5), when the gate electrode (3) has the multilayer structure, the second layer is arranged on the substrate (1) side of the first layer, and the thick

Abstract: A semiconductor device includes a substrate and a thin film transistor supported by the substrate. The thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer provided between the gate electrode and the oxide semiconductor layer, and source and drain electrodes electrically connected to the oxide semiconductor layer. The gate insulating layer includes a first portion which is covered with the oxide semiconductor layer and a second portion which is adjacent to the first portion and which is not covered with any of the oxide semiconductor layer, the source electrode and the drain electrode. The second portion is smaller in thickness than the first portion, and the difference in thickness between the second portion and the first portion is more than 0 nm and not more than 50 nm.

Abstract: A semiconductor device (100) includes: a substrate (10); and a thin film transistor (5) supported on the substrate, the thin film transistor including a gate electrode (12), an oxide semiconductor layer (18), a gate insulating layer (20) provided between the gate electrode and the oxide semiconductor layer, and a source electrode (14) and a drain electrode (16) electrically connected to the oxide semiconductor layer, wherein: the drain electrode is shaped so as to project toward the oxide semiconductor layer; a width W1 and a width W2 satisfy a relationship |W1?W2|?1 ?m, where the width W1 is a width of the oxide semiconductor layer in a channel width direction of the thin film transistor, and the width W2 is a width of the drain electrode in a direction perpendicular to a direction in which the drain electrode projects; and the width W1 and the width W2 are 3 ?m or more and 6 ?m or less.

Abstract: A semiconductor device (100A) includes: a substrate (1); a thin film transistor (101) whose active layer is an oxide semiconductor layer 5; at least one metal wiring layer including copper (7S, 7D); a metal oxide film including copper (8) arranged on an upper surface of the at least one metal wiring layer (7S, 7D); an insulating layer (11) covering at least one metal wiring layer with the metal oxide film (8) interposed therebetween; and a conductive layer (19) in direct contact with a portion of the at least one metal wiring layer, without the metal oxide film (8) interposed therebetween, in an opening formed in the insulating layer (11).

Abstract: A semiconductor device (100A) includes a substrate (101) and a thin film transistor (10) supported by the substrate. The thin film transistor includes a gate electrode (102), an oxide semiconductor layer (104), a gate insulating layer (103), a source electrode (105) and a drain electrode (106). The oxide semiconductor layer includes an upper semiconductor layer (104b) which is in contact with the source electrode and the drain electrode and which has a first energy gap, and a lower semiconductor layer (104a) which is provided under the upper semiconductor layer and which has a second energy gap that is smaller than the first energy gap. The source electrode and the drain electrode include a lower layer electrode (105a, 106a) which is in contact with the oxide semiconductor layer and which does not contain Cu, and a major layer electrode (105b, 106b) which is provided over the lower layer electrode and which contains Cu.

Abstract: A semiconductor device (200A) includes: a thin film transistor (201) including a gate electrode (3), an oxide semiconductor layer (5), a gate insulating layer (4), and a source electrode (7S) and a drain electrode (7D); an interlayer insulating layer (11) arranged so as to cover the thin film transistor (201) and to be in contact with a channel region (5c) of the thin film transistor (201); a transparent conductive layer (19) arranged on interlayer insulating layer (11), wherein: the source and drain electrodes (7) each include copper; a copper alloy oxide film (10) including copper and at least one metal element other than copper is arranged between the source and drain electrodes (7) and the interlayer insulating layer (11); the interlayer insulating layer (11) covers the drain electrode (7D) with the copper alloy oxide film (10) interposed therebetween; and in a contact hole (CH1) formed in the interlayer insulating layer (11), the transparent conductive layer (19) is in direct contact with the drain elect

Abstract: A semiconductor device (100A) includes: a thin film transistor (101) including a gate electrode (3), an oxide semiconductor layer (5), a gate insulating layer (4), and a source electrode (7S) and a drain electrode (7D); an interlayer insulating layer (11) arranged so as to cover the thin film transistor (101) and to be in contact with a channel region (5c) of the thin film transistor (101); and a transparent conductive layer (19) arranged on the interlayer insulating layer (11), wherein: the source electrode (7S) and the drain electrode (7D) each include a copper layer (7a); a copper oxide film (8) is further provided between the source and drain electrodes and the interlayer insulating layer (11); the interlayer insulating layer (11) covers the drain electrode (7D) with the copper oxide film (8) interposed therebetween; and in a contact hole (CH1) formed in the interlayer insulating layer (11), the transparent conductive layer (19) is in direct contact with the copper layer (7a) of the drain electrode (7D) w

Abstract: The semiconductor device of the present invention is provided with: source wiring lines that are formed on a substrate; light-shielding members that are in the same layer as the source wiring lines; a source insulating film that covers the source wiring lines and the like; holes that penetrate the source insulating film; channel region that are formed of an oxide semiconductor film that is formed on the source insulating film so as to overlap the light-shielding members; source electrode portions that are formed of the oxide semiconductor film, the resistance of which has been decreased, and that are connected to the source wiring lines via the holes; drain electrode portions that are formed of the oxide semiconductor film, the resistance of which has been decreased, and that oppose the source electrode portions with the channel region being interposed therebetween; gate insulating films that are formed on the channel region; and gate electrodes that are formed on the gate insulating films so as to overlap th

Abstract: An array board (a semiconductor device) 11b includes a display area TFT (a display area transistor) 17, a non-display area TFT (a non-display area transistor) 29, an upper insulator 31, and a lower insulator 30. The display area TFT 17 is arranged in a display area AA. The non-display area TFT 29 is arranged in a non-display area NAA. The upper insulator 31 is arranged in the non-display area NAA and formed from a second interlayer insulation film 41. The lower insulator 30 is arranged in the non-display area and formed from a first interlayer insulation film 39. The lower insulator 30 is arranged below the upper insulator 31 such that they are layered.

Abstract: An array board (a semiconductor device) 11b includes a display area TFT (a display area transistor) 17, a non-display area TFT (a non-display area transistor) 29, an upper insulator 31, and a lower insulator 30. The display area TFT 17 is arranged in a display area AA. The non-display area TFT 29 is arranged in a non-display area NAA. The upper insulator 31 is arranged in the non-display area NAA and formed from a second interlayer insulation film 41. The lower insulator 30 is arranged in the non-display area and formed from a first interlayer insulation film 39. The lower insulator 30 is arranged below the upper insulator 31 such that they are layered.

Abstract: The present invention provides an active matrix substrate including a thin film transistor that sufficiently achieves high reliability and a low capacitance, a production method for the active matrix substrate without an increase in the number of photomasks, a display device including the active matrix substrate, and a production method for the display device. The active matrix substrate of the present invention includes a thin film transistor that includes a semiconductor layer consisting of an oxide semiconductor. The active matrix substrate includes at least the semiconductor layer consisting of the oxide semiconductor, an etching stopper layer, and an interlayer insulating film formed from a spin-on-glass material. In the plan view of the principal surface of the substrate, the etching stopper layer covers at least part of the semiconductor layer, and the interlayer insulating film covers at least part of the etching stopper layer.

Abstract: An active matrix substrate (20a) includes a gate electrode (25) formed on an insulating substrate (10a), and a planarizing film (26) formed on the gate electrode (25) and made of a baked SOG material. The gate electrode (25) is a multilayer film including a first conductive film (27) formed on the insulating substrate (10a) and made of a metal except copper, a second conductive film (28) formed on the first conductive film (27) and made of copper, and a third conductive film (29) formed on the second conductive film (28) and made of the metal except copper.

Abstract: Disclosed is an active matrix substrate (5) on which pixels, each having a thin film transistor (18) and a pixel electrode (19) connected to the thin film transistor (18), are disposed in a matrix, and that includes a base material (5a) on which the pixels in a matrix are formed. In a contact hole portion (H), by anodically oxidizing a three-layered metal film (metal film) (21), an anodic oxidation film (29) is formed on the three-layered metal film (21) so as to fill a contact hole of a protective layer (27), with an end portion of the anodic oxidation film (29) being placed under an insulating layer (28). In the contact hole portion (H), the pixel electrode (19) and the three-layered metal film (21) are connected to each other via the anodic oxidation film (29).

Abstract: An active matrix substrate (20a) includes a gate electrode (25) formed on an insulating substrate (10a), and a planarizing film (26) formed on the gate electrode (25) and made of a baked SOG material. The gate electrode (25) is a multilayer film including a first conductive film (27) formed on the insulating substrate (10a) and made of a metal except copper, a second conductive film (28) formed on the first conductive film (27) and made of copper, and a third conductive film (29) formed on the second conductive film (28) and made of the metal except copper.

Abstract: Substrate material processing equipment includes: a substrate material conveying section receiving a substrate material from a first line and conveying it to a second line; a first substrate material dividing section dividing the substrate material; a substrate material recovery section recovering the substrate material from its start edge formed by division; a substrate material supply section supplying a substrate material to an end edge of the substrate material which is formed by division; a first substrate material joining section joining the end edge of the substrate material to a start edge of the substrate material supplied from the substrate material supply section; a second substrate material dividing section provided between the substrate material supply section and the first substrate material joining section; a third substrate material dividing section provided between the first line and the substrate material recovery section; and a second substrate material joining section joining a start edge

Abstract: Disclosed is an active matrix substrate (5) on which pixels, each having a thin film transistor (18) and a pixel electrode (19) connected to the thin film transistor (18), are disposed in a matrix, and that includes a base material (5a) on which the pixels in a matrix are formed. In a contact hole portion (H), by anodically oxidizing a three-layered metal film (metal film) (21), an anodic oxidation film (29) is formed on the three-layered metal film (21) so as to fill a contact hole of a protective layer (27), with an end portion of the anodic oxidation film (29) being placed under an insulating layer (28). In the contact hole portion (H), the pixel electrode (19) and the three-layered metal film (21) are connected to each other via the anodic oxidation film (29).

Abstract: An apparatus for manufacturing a semiconductor element includes processing chambers arranged to accommodate a flexible substrate which is step-transferred by one effective region each time; a first electrode and a second electrode which are provided in the processing chamber; and a mask portion having an opening so as to expose the effective region when each effective region of the flexible substrate is transferred between the first electrode and the second electrode.