Patents by Inventor Hisashi Adachi

Hisashi Adachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9479127
    Abstract: A power amplification apparatus generates a code for controlling the number of class D power amplifiers that are in operation among a plurality of class D power amplifiers, changes the duty ratio of a carrier wave signal in accordance with output voltage, and amplifies a transmission signal. A code for decreasing the number of class D power amplifiers in operation is generated when the duty ratio of the carrier wave signal is increased, while a code for increasing the number of class D power amplifiers in operation is generated when the duty ratio of the carrier wave signal is decreased.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: October 25, 2016
    Assignee: PANASONIC CORPORATION
    Inventors: Masahiro Kumagawa, Hisashi Adachi
  • Patent number: 9240812
    Abstract: A power amplification device includes: a first power-amplifier array including a plurality of first switching elements that constitute a class-D power amplifier for a higher bits; a second power-amplifier array including a plurality of second switching elements that constitute a class-D power amplifier for a lower bits; and a capacitor array including a plurality of capacitance elements. The second switching elements have a larger on-resistance than the first switching elements. The first power-amplifier array is arranged between the second power-amplifier array and the capacitor array.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: January 19, 2016
    Assignee: PANASONIC CORPORATION
    Inventors: Masahiro Kumagawa, Akinori Daimo, Hisashi Adachi
  • Patent number: 9148089
    Abstract: A transmitting apparatus and transmission method are capable of easily and correctly mixing an in-phase component and a quadrature-phase component in a quadrature modulator. A local signal with a duty ratio of 25% or smaller is generated without using frequency which is a multiple of frequency of the local signal. Without providing switches in series to the outputs of I and Q amplifiers, a duty ratio of 25% or less is obtained. for the local signal, and class-D unit amplifiers are operated such that one of the I amplifier and the Q amplifier is connected to the output side in any state regardless of whether an output power control signal is at an on-level or an off-level. In producing the 25% duty ratio, a local signal with a 50% duty ratio is converted so as to have a duty ratio of 25% by I and Q duty converters.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: September 29, 2015
    Assignee: Panasonic Corporation
    Inventors: Masakatsu Maeda, Masahiro Kumagawa, Hisashi Adachi, Akinori Daimo, Kenichi Mori
  • Patent number: 9130610
    Abstract: A transmission apparatus includes a digital amplifier having a plurality of class-D amplifiers connected in parallel to each other, each of the class-D amplifiers including a logic circuit that processes input signals from two input terminals and outputs the input signals to one of two output terminals, according to a selection signal, and including capacitors connected in series to the two output terminals, respectively, a first selection circuit that outputs either an in-phase component or a quadrature component of a transmission signal to the digital amplifier depending on the selection signal, and a second selection circuit that outputs either an in-phase component carrier signal or a quadrature component carrier signal to the digital amplifier depending on the selection signal.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: September 8, 2015
    Assignee: Panasonic Corporation
    Inventors: Masakatsu Maeda, Hisashi Adachi, Akinori Daimo, Kenichi Mori
  • Publication number: 20150249431
    Abstract: A power amplification apparatus generates a code for controlling the number of class D power amplifiers that are in operation among a plurality of class D power amplifiers, changes the duty ratio of a carrier wave signal in accordance with output voltage, and amplifies a transmission signal. A code for decreasing the number of class D power amplifiers in operation is generated when the duty ratio of the carrier wave signal is increased, while a code for increasing the number of class D power amplifiers in operation is generated when the duty ratio of the carrier wave signal is decreased.
    Type: Application
    Filed: February 19, 2015
    Publication date: September 3, 2015
    Inventors: MASAHIRO KUMAGAWA, HISASHI ADACHI
  • Publication number: 20150244324
    Abstract: A power amplification device includes: a first power-amplifier array including a plurality of first switching elements that constitute a class-D power amplifier for a higher bits; a second power-amplifier array including a plurality of second switching elements that constitute a class-D power amplifier for a lower bits; and a capacitor array including a plurality of capacitance elements. The second switching elements have a larger on-resistance than the first switching elements. The first power-amplifier array is arranged between the second power-amplifier array and the capacitor array.
    Type: Application
    Filed: February 19, 2015
    Publication date: August 27, 2015
    Inventors: MASAHIRO KUMAGAWA, AKINORI DAIMO, HISASHI ADACHI
  • Publication number: 20150236727
    Abstract: A transmission apparatus includes a digital amplifier having a plurality of class-D amplifiers connected in parallel to each other, each of the class-D amplifiers including a logic circuit that processes input signals from two input terminals and outputs the input signals to one of two output terminals, according to a selection signal, and including capacitors connected in series to the two output terminals, respectively, a first selection circuit that outputs either an in-phase component or a quadrature component of a transmission signal to the digital amplifier depending on the selection signal, and a second selection circuit that outputs either an in-phase component carrier signal or a quadrature component carrier signal to the digital amplifier depending on the selection signal.
    Type: Application
    Filed: January 28, 2015
    Publication date: August 20, 2015
    Inventors: MASAKATSU MAEDA, HISASHI ADACHI, AKINORI DAIMO, KENICHI MORI
  • Publication number: 20150180418
    Abstract: A transmitting apparatus and transmission method are capable of easily and correctly mixing an in-phase component and a quadrature-phase component in a quadrature modulator. A local signal with a duty ratio of 25% or smaller is generated without using frequency which is a multiple of frequency of the local signal. Without providing switches in series to the outputs of I and Q amplifiers, a duty ratio of 25% or less is obtained. for the local signal, and class-D unit amplifiers are operated such that one of the I amplifier and the Q amplifier is connected to the output side in any state regardless of whether an output power control signal is at an on-level or an off-level. In producing the 25% duty ratio, a local signal with a 50% duty ratio is converted so as to have a duty ratio of 25% by I and Q duty converters.
    Type: Application
    Filed: November 17, 2014
    Publication date: June 25, 2015
    Inventors: MASAKATSU MAEDA, MASAHIRO KUMAGAWA, HISASHI ADACHI, AKINORI DAIMO, KENICHI MORI
  • Patent number: 7973609
    Abstract: A frequency synthesizer includes a digitally-controlled oscillator and an oscillation frequency control unit. The digitally-controlled oscillator includes a loop-shaped transmission line path having an odd number of parallel portions in each of which two conductors are arranged in parallel to each other with a space therebetween, and an odd number of intersection portions in each of which two conductors intersect spatially, an active circuit coupled between the two conductors, and a first variable capacitance unit and a second variable capacitance unit. The oscillation frequency control unit includes a ?? modulation circuit for subjecting to ?? modulation a first control signal for switching a high capacitance state and a low capacitance state of a first variable capacitance element included in the first variable capacitance unit.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: July 5, 2011
    Assignee: Panasonic Corporation
    Inventors: Atsushi Ohara, Shinichiro Uemura, Hisashi Adachi
  • Patent number: 7944994
    Abstract: A data converter that converts an input signal to a signal to be inputted to an amplifier. Specifically, the data converter includes: an amplitude detection section that detects an amplitude level of the input signal; a region determination section that determines whether or not an input power to the amplifier is in a non-linear region of the amplifier based on the amplitude level of the input signal detected by the amplitude detection section; and a signal processing section that converts the input signal to a signal having a lower resolution than that of the input signal if the region determination section determines that the input power to the amplifier is in the non-linear region of the amplifier.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: May 17, 2011
    Assignee: Panasonic Corporation
    Inventors: Toru Matsuura, Hisashi Adachi
  • Patent number: 7925226
    Abstract: A transmission circuit capable of transmitting a modulated wave signal using polar modulation in a broad band and with low power consumption is provided. The transmission circuit generates an amplitude signal and a phase signal based on data to be transmitted, and separates the amplitude signal into a low-frequency amplitude signal and a high-frequency amplitude signal. The transmission circuit amplitude-modulates the phase signal in a broad band using the high-frequency amplitude signal in a high-frequency voltage control section 104 and an amplitude modulation section 105 and amplitude-modulates the phase signal into low power consumption using the low-frequency amplitude signal in a low-frequency voltage control section 106 and amplitude modulation section 107.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: April 12, 2011
    Assignee: Panasonic Corporation
    Inventors: Toru Matsuura, Hisashi Adachi
  • Patent number: 7876170
    Abstract: A voltage controlled oscillator 1, a variable frequency divider 2, a phase comparator 3, and a loop filter 4 form a Phase Locked Loop (PLL). A sigma-delta modulator 5 sigma-delta modulates data obtained by adding a fractional part M2 of the frequency division factor data with modulation data X by using an output signal of the variable frequency divider 2 as a clock. An output signal of the sigma-delta modulator 5 is added to an integral part M1 of the frequency division factor data, and the resultant data becomes effective frequency division factor data 13 of the variable frequency divider 2. An output signal of the sigma-delta modulator 5 also becomes control data 14 after passing through a D/A converter 6, a low-pass filter 7, and an amplitude adjustment circuit 8. The control data 14 is inputted into a frequency modulation terminal of the voltage controlled oscillator 1.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: January 25, 2011
    Assignee: Panasonic Corporation
    Inventors: Hisashi Adachi, Makoto Sakakura
  • Patent number: 7855588
    Abstract: A clock signal generation apparatus containing variable delay devices for varying the delay time of two-phase clock signals used in a load circuit that uses non-overlap clock signals; a non-overlap detector for detecting a non-overlap time in the H-level zones of the two-phase clock signals and outputting a detection signal corresponding to the non-overlap time; and a control signal generation section for generating a control signal that is used to control the variable delay devices on the basis of the detection signal from the non-overlap detector, and capable of securely generating the two-phase clock signals having an optimal non-overlap time while absorbing fluctuations due to temperature characteristics, power supply voltage characteristics and individual differences in components.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: December 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Masahiko Sagisaka, Hisashi Adachi, Taiji Akizuki
  • Patent number: 7855668
    Abstract: A multibit quantizer is provided, at its input terminals, with a variable gain circuit and an offset addition circuit to perform tracking control in which for each sampling time, the level of an offset signal of the offset addition circuit is adjusted based on output digital data of an output processing circuit and the preceding control signal of an offset control circuit so that the quantizer operates without causing a saturation operation. As a result, the output digital data, in which the number of bits is greater than the number of bits of the quantizer by the offset value controlled by the offset addition circuit, is outputted from the output processing circuit for each sampling time.
    Type: Grant
    Filed: August 29, 2009
    Date of Patent: December 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Taiji Akizuki, Masahiko Sagisaka, Hisashi Adachi
  • Patent number: 7817725
    Abstract: The present invention aims to provide a transmitter circuit that is capable of suppressing quantization noise and operating with a high efficiency, a data converter section 13 and a data conversion method for use therein, and a communications device using the same. The data converter section 13 of the present invention performs a predetermined data conversion operation on an input signal. The data converter section 13 includes: a signal processing section 133 for discretizing the input signal to produce a signal having a lower resolution magnitude-wise than that of the input signal; a subtractor section 134 for subtracting the input signal from the signal having a lower resolution to extract quantization noise; a filter 135 for extracting quantization noise near an intended wave frequency; and a subtractor section 136 for removing the quantization noise near the intended wave frequency from the signal having a lower resolution.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: October 19, 2010
    Assignee: Panasonic Corporation
    Inventors: Toru Matsuura, Hisashi Adachi
  • Publication number: 20100214142
    Abstract: A multibit quantizer is provided, at its input terminals, with a variable gain circuit and an offset addition circuit to perform tracking control in which for each sampling time, the level of an offset signal of the offset addition circuit is adjusted based on output digital data of an output processing circuit and the preceding control signal of an offset control circuit so that the quantizer operates without causing a saturation operation. As a result, the output digital data, in which the number of bits is greater than the number of bits of the quantizer by the offset value controlled by the offset addition circuit, is outputted from the output processing circuit for each sampling time.
    Type: Application
    Filed: August 29, 2009
    Publication date: August 26, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Taiji Akizuki, Masahiko Sagisaka, Hisashi Adachi
  • Patent number: 7777663
    Abstract: The present invention is intended to attain simplified circuit configuration and low current consumption in a discrete time amplifier circuit and an AD converter, to improve the convergence from the transient response state to the steady state of the amplifier circuit and to reduce noise and distortion owing to the variation in the output common-mode voltage. The discrete time amplifier circuit and the AD converter are provided with a switched-capacitor common-mode feedback (CMFB) circuit capable of detecting and feeding back the output common-mode voltage at every sampling timing in the case that the circuit operates at double sampling timing (every ½ cycle).
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: August 17, 2010
    Assignee: Panasonic Corporation
    Inventors: Taiji Akizuki, Tomoaki Maeda, Hisashi Adachi
  • Patent number: 7725082
    Abstract: Radio communication apparatus comprising an antenna, a transmitting circuit of outputting a transmitting signal in a first frequency band. A duplexer connected to the antenna and having a single-phase input terminal and a balanced output terminal, conveying the transmitting signal inputted to the single-phase input terminal to the antenna. The duplexer outputs a receiving signal in a second frequency band different from the first frequency band received from the antenna substantially as a differential signal from the balanced output terminal. A receiving circuit connected to the balanced output terminal and having a circuit in which a gain of a signal of a differential component is higher than that of a signal of an in-phase component, or a loss of the signal of the differential component is lower than that of the signal of the in-phase component.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: May 25, 2010
    Assignee: Panasonic Corp.
    Inventors: Toshifumi Nakatani, Atsushi Yamamoto, Hisashi Adachi
  • Patent number: 7702299
    Abstract: The amplitude modulator comprises: an angle modulator for angle-modulating a phase signal to be inputted; a waveform shaping means in which, (1) when the magnitude of an amplitude signal to be inputted becomes smaller than a first prescribed value, a waveform of the amplitude signal is shaped so that the magnitude of the amplitude signal of the portion which becomes small becomes the first prescribed value; and/or (2) the waveform shaping means in which, when the magnitude of the amplitude signal to be inputted becomes larger than the second prescribed value which is larger than the first prescribed value, the waveform of the amplitude signal is shaped so that the magnitude of the amplitude signal of the portion which becomes larger becomes the second prescribed value; and an amplitude modulator for amplitude modulating the signal of the output of the angle modulator by the signal of the output of the waveform shaping means.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: April 20, 2010
    Assignee: Panasonic Corporation
    Inventors: Toru Matsuura, Hisashi Adachi, Masaharu Udagawa
  • Patent number: 7696830
    Abstract: The digital controlled oscillator includes a variable capacitance section having a first capacitor array of a plurality of first variable capacitors and a second capacitor array of a plurality of second variable capacitors, and generates a signal having an oscillation frequency corresponding to the capacitance value of the variable capacitance section. The first capacitance change amount in the individual first variable capacitors is a value obtained by multiplying the second capacitance change amount in the individual second variable capacitors by an integer equal to or more than 2, and the number of second variable capacitors is equal to or more than a value obtained by subtracting 1 from the integer equal to or more than 2.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: April 13, 2010
    Assignee: Panasonic Corporation
    Inventors: Atsushi Ohara, Hisashi Adachi