Abstract: A flying body identification system according to the present example embodiment includes: a flying body; a communication terminal configured to obtain an airframe ID of the flying body; and a control system configured to control an operation of the flying body. The control system is also configured to: manage the airframe ID and a plurality of pieces of information regarding the flying body indicated by the airframe ID so as to be associated with each other; select, in a case where an inquiry message containing the airframe ID and an authority level assigned to the communication terminal is received from the communication terminal, information to be transmitted to the communication terminal among the plurality of pieces of information regarding the flying body associated with the airframe ID in accordance with the authority level of the communication terminal; and transmit the selected information to the communication terminal.

Abstract: An air traffic control system (31) according to the present disclosure includes a communication unit (4) configured to receive, from a communication terminal (40), an image including a flying object (2) captured by the communication terminal (40) and position information about the communication terminal (40), an estimation unit (8) configured to estimate a position of the flying object (2) using background information and the position information included in the image, and an identification unit (5) configured to identify the flying object (2) using the estimated position of the flying object (2). The communication unit (4) transmits information about the identified flying object (2) to the communication terminal (40).

Abstract: A flying object according to example embodiments includes an airframe ID control unit configured to hold an airframe ID of the flying object changed according to a predetermined change pattern, and a communication unit configured to transmit the airframe ID. An air traffic control system according to the example embodiments includes a communication unit configured to acquire a first airframe ID and position information transmitted from a flying object, and an identification unit configured to identify the flying object using the first airframe ID. When the communication unit acquires a second airframe ID different from the first airframe ID after acquiring the first airframe ID, the identification unit determines whether or not the second airframe ID indicates the flying object based on a change between the position information at the time of acquiring the first airframe ID and the position information at the time of acquiring the second airframe ID.

Abstract: A power amplification apparatus generates a code for controlling the number of class D power amplifiers that are in operation among a plurality of class D power amplifiers, changes the duty ratio of a carrier wave signal in accordance with output voltage, and amplifies a transmission signal. A code for decreasing the number of class D power amplifiers in operation is generated when the duty ratio of the carrier wave signal is increased, while a code for increasing the number of class D power amplifiers in operation is generated when the duty ratio of the carrier wave signal is decreased.

Abstract: A power amplification device includes: a first power-amplifier array including a plurality of first switching elements that constitute a class-D power amplifier for a higher bits; a second power-amplifier array including a plurality of second switching elements that constitute a class-D power amplifier for a lower bits; and a capacitor array including a plurality of capacitance elements. The second switching elements have a larger on-resistance than the first switching elements. The first power-amplifier array is arranged between the second power-amplifier array and the capacitor array.

Abstract: A transmitting apparatus and transmission method are capable of easily and correctly mixing an in-phase component and a quadrature-phase component in a quadrature modulator. A local signal with a duty ratio of 25% or smaller is generated without using frequency which is a multiple of frequency of the local signal. Without providing switches in series to the outputs of I and Q amplifiers, a duty ratio of 25% or less is obtained. for the local signal, and class-D unit amplifiers are operated such that one of the I amplifier and the Q amplifier is connected to the output side in any state regardless of whether an output power control signal is at an on-level or an off-level. In producing the 25% duty ratio, a local signal with a 50% duty ratio is converted so as to have a duty ratio of 25% by I and Q duty converters.

Abstract: A transmission apparatus includes a digital amplifier having a plurality of class-D amplifiers connected in parallel to each other, each of the class-D amplifiers including a logic circuit that processes input signals from two input terminals and outputs the input signals to one of two output terminals, according to a selection signal, and including capacitors connected in series to the two output terminals, respectively, a first selection circuit that outputs either an in-phase component or a quadrature component of a transmission signal to the digital amplifier depending on the selection signal, and a second selection circuit that outputs either an in-phase component carrier signal or a quadrature component carrier signal to the digital amplifier depending on the selection signal.

Abstract: A power amplification apparatus generates a code for controlling the number of class D power amplifiers that are in operation among a plurality of class D power amplifiers, changes the duty ratio of a carrier wave signal in accordance with output voltage, and amplifies a transmission signal. A code for decreasing the number of class D power amplifiers in operation is generated when the duty ratio of the carrier wave signal is increased, while a code for increasing the number of class D power amplifiers in operation is generated when the duty ratio of the carrier wave signal is decreased.

Abstract: A power amplification device includes: a first power-amplifier array including a plurality of first switching elements that constitute a class-D power amplifier for a higher bits; a second power-amplifier array including a plurality of second switching elements that constitute a class-D power amplifier for a lower bits; and a capacitor array including a plurality of capacitance elements. The second switching elements have a larger on-resistance than the first switching elements. The first power-amplifier array is arranged between the second power-amplifier array and the capacitor array.

Abstract: A transmission apparatus includes a digital amplifier having a plurality of class-D amplifiers connected in parallel to each other, each of the class-D amplifiers including a logic circuit that processes input signals from two input terminals and outputs the input signals to one of two output terminals, according to a selection signal, and including capacitors connected in series to the two output terminals, respectively, a first selection circuit that outputs either an in-phase component or a quadrature component of a transmission signal to the digital amplifier depending on the selection signal, and a second selection circuit that outputs either an in-phase component carrier signal or a quadrature component carrier signal to the digital amplifier depending on the selection signal.

Abstract: A transmitting apparatus and transmission method are capable of easily and correctly mixing an in-phase component and a quadrature-phase component in a quadrature modulator. A local signal with a duty ratio of 25% or smaller is generated without using frequency which is a multiple of frequency of the local signal. Without providing switches in series to the outputs of I and Q amplifiers, a duty ratio of 25% or less is obtained. for the local signal, and class-D unit amplifiers are operated such that one of the I amplifier and the Q amplifier is connected to the output side in any state regardless of whether an output power control signal is at an on-level or an off-level. In producing the 25% duty ratio, a local signal with a 50% duty ratio is converted so as to have a duty ratio of 25% by I and Q duty converters.

Abstract: A frequency synthesizer includes a digitally-controlled oscillator and an oscillation frequency control unit. The digitally-controlled oscillator includes a loop-shaped transmission line path having an odd number of parallel portions in each of which two conductors are arranged in parallel to each other with a space therebetween, and an odd number of intersection portions in each of which two conductors intersect spatially, an active circuit coupled between the two conductors, and a first variable capacitance unit and a second variable capacitance unit. The oscillation frequency control unit includes a ?? modulation circuit for subjecting to ?? modulation a first control signal for switching a high capacitance state and a low capacitance state of a first variable capacitance element included in the first variable capacitance unit.

Abstract: A data converter that converts an input signal to a signal to be inputted to an amplifier. Specifically, the data converter includes: an amplitude detection section that detects an amplitude level of the input signal; a region determination section that determines whether or not an input power to the amplifier is in a non-linear region of the amplifier based on the amplitude level of the input signal detected by the amplitude detection section; and a signal processing section that converts the input signal to a signal having a lower resolution than that of the input signal if the region determination section determines that the input power to the amplifier is in the non-linear region of the amplifier.

Abstract: A transmission circuit capable of transmitting a modulated wave signal using polar modulation in a broad band and with low power consumption is provided. The transmission circuit generates an amplitude signal and a phase signal based on data to be transmitted, and separates the amplitude signal into a low-frequency amplitude signal and a high-frequency amplitude signal. The transmission circuit amplitude-modulates the phase signal in a broad band using the high-frequency amplitude signal in a high-frequency voltage control section 104 and an amplitude modulation section 105 and amplitude-modulates the phase signal into low power consumption using the low-frequency amplitude signal in a low-frequency voltage control section 106 and amplitude modulation section 107.

Abstract: A voltage controlled oscillator 1, a variable frequency divider 2, a phase comparator 3, and a loop filter 4 form a Phase Locked Loop (PLL). A sigma-delta modulator 5 sigma-delta modulates data obtained by adding a fractional part M2 of the frequency division factor data with modulation data X by using an output signal of the variable frequency divider 2 as a clock. An output signal of the sigma-delta modulator 5 is added to an integral part M1 of the frequency division factor data, and the resultant data becomes effective frequency division factor data 13 of the variable frequency divider 2. An output signal of the sigma-delta modulator 5 also becomes control data 14 after passing through a D/A converter 6, a low-pass filter 7, and an amplitude adjustment circuit 8. The control data 14 is inputted into a frequency modulation terminal of the voltage controlled oscillator 1.

Abstract: A multibit quantizer is provided, at its input terminals, with a variable gain circuit and an offset addition circuit to perform tracking control in which for each sampling time, the level of an offset signal of the offset addition circuit is adjusted based on output digital data of an output processing circuit and the preceding control signal of an offset control circuit so that the quantizer operates without causing a saturation operation. As a result, the output digital data, in which the number of bits is greater than the number of bits of the quantizer by the offset value controlled by the offset addition circuit, is outputted from the output processing circuit for each sampling time.

Abstract: A clock signal generation apparatus containing variable delay devices for varying the delay time of two-phase clock signals used in a load circuit that uses non-overlap clock signals; a non-overlap detector for detecting a non-overlap time in the H-level zones of the two-phase clock signals and outputting a detection signal corresponding to the non-overlap time; and a control signal generation section for generating a control signal that is used to control the variable delay devices on the basis of the detection signal from the non-overlap detector, and capable of securely generating the two-phase clock signals having an optimal non-overlap time while absorbing fluctuations due to temperature characteristics, power supply voltage characteristics and individual differences in components.

Abstract: The present invention aims to provide a transmitter circuit that is capable of suppressing quantization noise and operating with a high efficiency, a data converter section 13 and a data conversion method for use therein, and a communications device using the same. The data converter section 13 of the present invention performs a predetermined data conversion operation on an input signal. The data converter section 13 includes: a signal processing section 133 for discretizing the input signal to produce a signal having a lower resolution magnitude-wise than that of the input signal; a subtractor section 134 for subtracting the input signal from the signal having a lower resolution to extract quantization noise; a filter 135 for extracting quantization noise near an intended wave frequency; and a subtractor section 136 for removing the quantization noise near the intended wave frequency from the signal having a lower resolution.

Abstract: A multibit quantizer is provided, at its input terminals, with a variable gain circuit and an offset addition circuit to perform tracking control in which for each sampling time, the level of an offset signal of the offset addition circuit is adjusted based on output digital data of an output processing circuit and the preceding control signal of an offset control circuit so that the quantizer operates without causing a saturation operation. As a result, the output digital data, in which the number of bits is greater than the number of bits of the quantizer by the offset value controlled by the offset addition circuit, is outputted from the output processing circuit for each sampling time.

Abstract: The present invention is intended to attain simplified circuit configuration and low current consumption in a discrete time amplifier circuit and an AD converter, to improve the convergence from the transient response state to the steady state of the amplifier circuit and to reduce noise and distortion owing to the variation in the output common-mode voltage. The discrete time amplifier circuit and the AD converter are provided with a switched-capacitor common-mode feedback (CMFB) circuit capable of detecting and feeding back the output common-mode voltage at every sampling timing in the case that the circuit operates at double sampling timing (every ½ cycle).