Patents by Inventor Hisashi Ishida
Hisashi Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11890746Abstract: A ground reaction force load difference calculation unit configured to calculate a ground reaction force load difference that is an amount of a load relief for a user, on the basis of a first measured value that a weight, based on a weight of the user and a weight of the load reduction device that reduces a load on the user and has a mechanism that holds luggage and is at least worn by the user, is transmitted to a ground contact surface and of a second measured value that a weight based on the weight of the user is transmitted to the ground contact surface; and a torque control unit configured to control, on the basis of the ground reaction force load difference, torque that is output by the load reduction device to reduce the load on the user at an joint of each leg of the user.Type: GrantFiled: November 8, 2019Date of Patent: February 6, 2024Assignee: NEC CORPORATIONInventors: Tadashi Ookoba, Hisashi Ishida
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Publication number: 20220016785Abstract: A ground reaction force load difference calculation unit configured to calculate a ground reaction force load difference that is an amount of a load relief for a user, on the basis of a first measured value that a weight, based on a weight of the user and a weight of the load reduction device that reduces a load on the user and has a mechanism that holds luggage and is at least worn by the user, is transmitted to a ground contact surface and of a second measured value that a weight based on the weight of the user is transmitted to the ground contact surface; and a torque control unit configured to control, on the basis of the ground reaction force load difference, torque that is output by the load reduction device to reduce the load on the user at an joint of each leg of the user.Type: ApplicationFiled: November 8, 2019Publication date: January 20, 2022Applicant: NEC CorporationInventors: Tadashi OOKOBA, Hisashi ISHIDA
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Patent number: 11207003Abstract: Provided is to determine a walking state when a target person uses a stick. A walking state determination device according to an embodiment of the present invention includes: an acquisition unit that acquires feature information indicating a feature of a motion of a target person when using a stick, based on first measurement data acquired from a first sensor installed at the stick and second measurement data acquired from a second sensor installed at the target person; and a determination unit that determines a walking state of the target person, based on the acquired feature information.Type: GrantFiled: June 29, 2017Date of Patent: December 28, 2021Assignee: NEC CORPORATIONInventors: Kenichiro Fukushi, Hisashi Ishida, Takeo Nozaki
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Publication number: 20210203200Abstract: In the present invention a rotor core is formed by multiple divided cores that are separated from one another, and side core plates that link the outer circumferential ends of the divided cores in the circumferential direction. Slits into which magnets are inserted are maintained between the divided cores. The rotor core and a rotary shaft are coupled to one another by a molded resin, and the molded resin covers protrusions which are on both sides in the circumferential direction at the inner circumferential end of each divided core.Type: ApplicationFiled: March 17, 2017Publication date: July 1, 2021Applicant: MITSUBA CorporationInventors: Yuichi SHIONO, Masanori SATO, Hisashi ISHIDA, Tohru YUMOTO
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Patent number: 10776945Abstract: Provided are a reference scale and dimension measurement system that make it possible to maintain accurate measurement even if the reference scale is not disposed or projected on a measurement surface.Type: GrantFiled: July 19, 2016Date of Patent: September 15, 2020Assignee: NEC CORPORATIONInventors: Kenichiro Fukushi, Manabu Kusumoto, Yoshio Kameda, Hisashi Ishida, Chenpin Hsu, Takeo Nozaki
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Publication number: 20190150796Abstract: Provided is to determine a walking state when a target person uses a stick. A walking state determination device according to an embodiment of the present invention includes: an acquisition unit that acquires feature information indicating a feature of a motion of a target person when using a stick, based on first measurement data acquired from a first sensor installed at the stick and second measurement data acquired from a second sensor installed at the target person; and a determination unit that determines a walking state of the target person, based on the acquired feature information.Type: ApplicationFiled: June 29, 2017Publication date: May 23, 2019Applicant: NEC CorporationInventors: Kenichiro FUKUSHI, Hisashi ISHIDA, Takeo NOZAKI
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Publication number: 20180225843Abstract: Provided are a reference scale and dimension measurement system that make it possible to maintain accurate measurement even if the reference scale is not disposed or projected on a measurement surface.Type: ApplicationFiled: July 19, 2016Publication date: August 9, 2018Applicant: NEC CorporationInventors: Kenichiro FUKUSHI, Manabu KUSUMOTO, Yoshio KAMEDA, Hisashi ISHIDA, Chenpin HSU, Takeo NOZAKI
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Patent number: 9830420Abstract: A design support device having a permissible power supply fluctuation deriving unit and a target impedance deriving unit. The permissible power supply fluctuation deriving unit derives the fluctuation in the power supply voltage that is permissible on the basis of jitter-voltage correlation information, which indicates the correlation between the power supply voltage fluctuation generated in an I/O buffer and the jitter generated by the power supply voltage fluctuations, and jitter constraint information, which is for stably transmitting a signal, for the generated jitter. The target impedance deriving unit derives a target impedance in the permissible range of impedance for a power supply circuit, on the basis of information on the signal operating current flowing through the power supply circuit of the I/O buffer, and the power supply voltage fluctuation.Type: GrantFiled: January 14, 2014Date of Patent: November 28, 2017Assignee: NEC CorporationInventors: Masashi Ogawa, Manabu Kusumoto, Hisashi Ishida
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Patent number: 9653416Abstract: A method of manufacturing a semiconductor substrate includes a device-forming process of forming a plurality of device areas in a substrate section, a first wiring process of forming circuit wirings connected to the plurality of device areas, an electrode pad-forming process of forming a plurality of electrode pads, a second wiring process of forming a potential adjustment wiring electrically connecting at least a part of the electrode pads, an electrode-forming process of forming electrode bodies on the electrode pads by electroless plating after the second wiring process, and a potential adjustment-releasing process of releasing a connection by the potential adjustment wiring after the electrode-forming process.Type: GrantFiled: February 16, 2016Date of Patent: May 16, 2017Assignee: OLYMPUS CORPORATIONInventors: Chihiro Migita, Hisashi Ishida, Yoshiaki Takemoto
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Patent number: 9536033Abstract: Provided are an EMI characteristic derivation unit which derives an EMI characteristic radiated from a cable based on design information of a circuit board connected with the cable; a determination standard database which stores an EMI tolerance condition which is a tolerance condition for the EMI characteristic; an EMI condition determination unit which determines whether the EMI characteristic satisfies the EMI tolerance condition; an improvement effect database which stores a modification guideline to modify a configuration of the circuit board necessary to satisfy the EMI tolerance condition when the EMI characteristic does not satisfy the EMI tolerance condition and an improvement effect corresponding to the modification guideline; a restriction item database which stores a restriction item applied when the configuration of the board is modified; and a configuration modification unit which performs the configuration modification of the board in accordance with the modification guideline and the restrictiType: GrantFiled: September 18, 2013Date of Patent: January 3, 2017Assignee: NEC CORPORATIONInventors: Masashi Ogawa, Manabu Kusumoto, Hisashi Ishida, Ken Morishita, Masashi Kawakami
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Publication number: 20160163664Abstract: A method of manufacturing a semiconductor substrate includes a device-forming process of forming a plurality of device areas in a substrate section, a first wiring process of forming circuit wirings connected to the plurality of device areas, an electrode pad-forming process of forming a plurality of electrode pads, a second wiring process of forming a potential adjustment wiring electrically connecting at least a part of the electrode pads, an electrode-forming process of forming electrode bodies on the electrode pads by electroless plating after the second wiring process, and a potential adjustment-releasing process of releasing a connection by the potential adjustment wiring after the electrode-forming process.Type: ApplicationFiled: February 16, 2016Publication date: June 9, 2016Applicant: OLYMPUS CORPORATIONInventors: Chihiro Migita, Hisashi Ishida, Yoshiaki Takemoto
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Patent number: 9342649Abstract: To specify high-risk error positions in consideration of effects of electromagnetic noise flowing through a printed wiring board. A design rule check system (1) includes a pattern information acquisition unit (11) for acquiring a layout pattern of a board to be checked, a design rule check unit (12) for carrying out a design rule check on the layout pattern, a current calculation unit (13) for calculating distribution of noise current values on the board based on the layout pattern, a weighting unit (14) for adding a weight to a result of the design rule check according to the magnitude of the noise current values calculated by the current calculation unit (13) and corresponding to each error position detected through the design rule check, and an error information generation unit (15) which generates information indicating a risk level of each error position based on the weight.Type: GrantFiled: October 18, 2012Date of Patent: May 17, 2016Assignee: NEC CORPORATIONInventors: Ken Morishita, Hisashi Ishida
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Patent number: 9320141Abstract: The present invention provides a wiring structure that easily achieves a wiring part having a three-dimensional shape with high connection reliability and high signal quality. A wiring structure (10) according to the present invention includes one or a plurality of cables (18), a fiber (12) forming a mesh-like braiding fabric together with the cable (18), cable connectors (13, 17) formed at ends of the cable (18), and modules (14, 15) connected to the cable connectors (13, 17), the modules receiving or outputting signals through the cable.Type: GrantFiled: April 28, 2010Date of Patent: April 19, 2016Assignee: NEC CorporationInventor: Hisashi Ishida
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Patent number: 9313877Abstract: A first interconnect substrate includes a first conductor pattern. A second interconnect substrate includes a second conductor pattern. At least a portion of the second conductor pattern is formed in a region opposite the first conductor pattern. At least either the first conductor pattern or the second conductor pattern has a repeated structure. The first conductor pattern and the second conductor pattern constitute at least a portion of an electromagnetic band gap (EBG) structure.Type: GrantFiled: October 20, 2010Date of Patent: April 12, 2016Assignee: NEC CorporationInventor: Hisashi Ishida
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Publication number: 20150363538Abstract: A design support device having a permissible power supply fluctuation deriving unit and a target impedance deriving unit. The permissible power supply fluctuation deriving unit derives the fluctuation in the power supply voltage that is permissible on the basis of jitter-voltage correlation information, which indicates the correlation between the power supply voltage fluctuation generated in an I/O buffer and the jitter generated by the power supply voltage fluctuations, and jitter constraint information, which is for stably transmitting a signal, for the generated jitter. The target impedance deriving unit derives a target impedance in the permissible range of impedance for a power supply circuit, on the basis of information on the signal operating current flowing through the power supply circuit of the I/O buffer, and the power supply voltage fluctuation.Type: ApplicationFiled: January 14, 2014Publication date: December 17, 2015Applicant: NEC CorporationInventors: Masashi OGAWA, Manabu KUSUMOTO, Hisashi ISHIDA
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Publication number: 20150286758Abstract: Provided is a circuit analysis system using a circuit simulation model generation method such that, in a circuit including an LSI, signal characteristics and power supply characteristics can be analyzed accurately and in a short time. Provided is a circuit simulation device characterized by having: an input device (21) that inputs I-V characteristics, V-T characteristics, operating frequency, and operation pattern of a semiconductor integrated device; a simplified LSI model generation unit (22) that generates a simplified LSI model of the semiconductor integrated device on the basis of the contents of input from the input device (21); and an operating unit (25) that analyzes a circuit including the simplified LSI model.Type: ApplicationFiled: June 25, 2013Publication date: October 8, 2015Applicant: NEC CorporationInventors: Masashi Kawakami, Manabu Kusumoto, Masashi Ogawa, Hisashi Ishida
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Publication number: 20150286770Abstract: To specify high-risk error positions in consideration of effects of electromagnetic noise flowing through a printed wiring board. A design rule check system (1) includes a pattern information acquisition unit (11) for acquiring a layout pattern of a board to be checked, a design rule check unit (12) for carrying out a design rule check on the layout pattern, a current calculation unit (13) for calculating distribution of noise current values on the board based on the layout pattern, a weighting unit (14) for adding a weight to a result of the design rule check according to the magnitude of the noise current values calculated by the current calculation unit (13) and corresponding to each error position detected through the design rule check, and an error information generation unit (15) which generates information indicating a risk level of each error position based on the weight.Type: ApplicationFiled: October 18, 2012Publication date: October 8, 2015Inventors: Ken Morishita, Hisashi Ishida
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Publication number: 20150234972Abstract: Provided are an EMI characteristic derivation unit which derives an EMI characteristic radiated from a cable based on design information of a circuit board connected with the cable; a determination standard database which stores an EMI tolerance condition which is a tolerance condition for the EMI characteristic; an EMI condition determination unit which determines whether the EMI characteristic satisfies the EMI tolerance condition; an improvement effect database which stores a modification guideline to modify a configuration of the circuit board necessary to satisfy the EMI tolerance condition when the EMI characteristic does not satisfy the EMI tolerance condition and an improvement effect corresponding to the modification guideline; a restriction item database which stores a restriction item applied when the configuration of the board is modified; and a configuration modification unit which performs the configuration modification of the board in accordance with the modification guideline and the restrictiType: ApplicationFiled: September 18, 2013Publication date: August 20, 2015Applicant: NEC CorporationInventors: Masashi Ogawa, Manabu Kusumoto, Hisashi Ishida, Ken Morishita, Masashi Kawakami
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Patent number: 9027991Abstract: A racing bucket seat and a cooling system for racing cars is capable of effectively suppressing the rise of a driver's body temperature, meeting safety regulations. The racing bucket seat includes a plurality of shell through holes formed in a seat shell, an outer shell fixed on the seat shell to cover the shell through holes from a rear side of the seat shell and formed with a layer-like flow passage between the outer shell and a rear surface of the seat shell, and an air intake port introducing the air into the flow passage.Type: GrantFiled: January 8, 2010Date of Patent: May 12, 2015Assignee: Nissan Motorsports International Co., Ltd.Inventors: Hisashi Ishida, Yutaka Suzuki, Daisuke Takezaki, Shohei Ezaki
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Publication number: 20150005972Abstract: An electric power system tree display system includes: a specification information storing unit for storing specification information of the mounted parts; a tree information creating unit that reads out the specification information corresponding to design information input from the outside, from the specification information storing unit to prepare system tree information of the mounted parts connected by the electric power paths and determines electric power to be supplied to the mounted parts for each of the electric power paths, based on the read out specification information to prepare characteristic value information on the electric power paths; and a display unit for displaying the characteristic value information superposed on the system tree information.Type: ApplicationFiled: November 29, 2012Publication date: January 1, 2015Applicant: NEC CORPORATIONInventors: Hisashi Ishida, Risato Ohhira