Patents by Inventor Hisashi Kaneko

Hisashi Kaneko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8456186
    Abstract: A reliability evaluation test apparatus of this invention includes a wafer storage section which stores a wafer in a state wherein the electrode pads of a number of devices formed on the wafer and the bumps of a contactor are totally in electrical contact with each other. The wafer storage section transmits/receives a test signal to/from a measurement section and has a hermetic and heat insulating structure. The wafer storage section has a pressure mechanism which presses the contactor and a heating mechanism which directly heats the wafer totally in contact with the contactor to a predetermined high temperature. The reliability of an interconnection film and insulating film formed on the semiconductor wafer are evaluated under an accelerated condition.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: June 4, 2013
    Assignees: Tokyo Electron Limited, Ibiden Co., Ltd.
    Inventors: Kiyoshi Takekoshi, Hisatomi Hosaka, Junichi Hagihara, Kunihiko Hatsushika, Takamasa Usui, Hisashi Kaneko, Nobuo Hayasaka, Yoshiyuki Ido
  • Patent number: 8232197
    Abstract: An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: July 31, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Honda, Kaori Yomogihara, Kazuhiro Murakami, Masanori Numano, Takahito Nagamatsu, Hideaki Harakawa, Hideto Matsuyama, Hirokazu Ezawa, Hisashi Kaneko
  • Patent number: 7996813
    Abstract: A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: August 9, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaaki Hatano, Motoya Okazaki, Junichi Wada, Takeshi Nishioka, Hisashi Kaneko, Takeshi Fujimaki, Kazuyuki Higashi, Kenji Yoshida, Noriaki Matsunaga
  • Patent number: 7921401
    Abstract: A stress analysis method is provided: including dividing, by using a division unit, an inside of a chip into a plurality of analysis areas, deriving, by using a composite property derivation unit, a composite property into which physical property values of a plurality of materials included in an analysis area are compounded, about each of the plurality of analysis areas on the basis of wiring structure data for each of the plurality of analysis areas, and creating, by using a stress analysis unit, a three-dimensional model of a finite element method which uses each analysis area as an element, to apply the composite property to each element, and to perform a stress analysis.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: April 5, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sachiyo Ito, Masahiko Hasunuma, Hisashi Kaneko
  • Publication number: 20100115479
    Abstract: A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.
    Type: Application
    Filed: January 7, 2010
    Publication date: May 6, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaaki Hatano, Motoya Okazaki, Junichi Wada, Takeshi Nishioka, Hisashi Kaneko, Takeshi Fujimaki, Kazuyuki Higashi, Kanji Yoshida, Noriaki Matsunaga
  • Patent number: 7675183
    Abstract: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: March 9, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Toyoda, Mitsuhiro Nakao, Masahiko Hasunuma, Hisashi Kaneko, Atsuko Sakata, Toshiaki Komukai
  • Patent number: 7667332
    Abstract: A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.
    Type: Grant
    Filed: November 3, 2005
    Date of Patent: February 23, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaaki Hatano, Motoya Okazaki, Junichi Wada, Takeshi Nishioka, Hisashi Kaneko, Takeshi Fujimaki, Kazuyuki Higashi, Kenji Yoshida, Noriaki Matsunaga
  • Publication number: 20100003816
    Abstract: An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.
    Type: Application
    Filed: September 9, 2009
    Publication date: January 7, 2010
    Inventors: Makoto Honda, Kaori Yomogihara, Kazuhiro Murakami, Masanori Numano, Takahito Nagamatsu, Hideaki Harakawa, Hideto Matsuyama, Hirokazu Ezawa, Hisashi Kaneko
  • Patent number: 7635646
    Abstract: A method for fabricating a semiconductor device, includes forming a first dielectric film above a substrate, forming an opening in the first dielectric film, forming a catalytic characteristic film using at least one of a metal having catalytic characteristics and a conductive oxide having catalytic characteristics as its material on sidewalls and at a bottom of the opening, depositing a conductive material film using a conductive material in the opening in which the catalytic characteristic film is formed on the sidewalls and at the bottom, removing the catalytic characteristic film formed on the sidewalls of the opening, and forming a second dielectric film above the first dielectric film and the conductive material film after the removing.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: December 22, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiichi Omoto, Hisashi Kaneko, Masahiko Hasunuma
  • Publication number: 20090290261
    Abstract: A carriage block body is coupled to a support shaft for relative rotation. A carriage arm extends from the carriage block body along an imaginary plane perpendicular to the longitudinal axis of the support shaft. A head suspension is attached to the tip end of the carriage arm. A wiring extends outside the contour of the head suspension along the side of the carriage arm. A projection protrudes from the side of the carriage arm. An adhesive is utilized to bond the wiring to the projection. Even though airflow generated along the surface of a rotating disk medium collides against the carriage arm, the wiring is reliably prevented from fluttering outside the contour of the head suspension. The vibration of the wiring is thus significantly suppressed. The carriage arm is prevented from vibrating.
    Type: Application
    Filed: January 22, 2009
    Publication date: November 26, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Hisashi Kaneko, Keiji Aruga
  • Patent number: 7608537
    Abstract: A method for fabricating a semiconductor device, includes forming an opening in a first film, embedding an alignment mark material for alignment with an upper layer in the opening, forming a second film on the first film in which the alignment mark material is embedded, irradiating the second film formed in a predetermined region including a position where the alignment mark material is embedded with a processing light, thereby to remove the second film to an extent that a portion of the second film remains in the predetermined region, and exposing the portion of the second film remaining in the predetermined region to an etching environment for etching the second film.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: October 27, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mie Matsuo, Hisashi Kaneko
  • Patent number: 7605076
    Abstract: An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: October 20, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Honda, Kaori Yomogihara, Kazuhiro Murakami, Masanori Numano, Takahito Nagamatsu, Hideaki Harakawa, Hideto Matsuyama, Hirokazu Ezawa, Hisashi Kaneko
  • Patent number: 7601638
    Abstract: A method for manufacturing a semiconductor device includes forming, on a substrate having a recessed portion on a surface, a plating film which is at least buried in the recessed portion and has a higher impurity concentration in an upper portion than in a lower portion, thermally treating the plating film, and removing the thermally treated plating film except for a portion buried in the recessed portion.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: October 13, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Hasunuma, Hisashi Kaneko, Hiroshi Toyoda
  • Patent number: 7575664
    Abstract: A cathode potential is applied to a conductive layer formed on a substrate having a depression pattern. A plating solution in electrical contact with an anode is supplied to the conductive layer to form a plating film on the conductive layer. At this time, the plating solution is supplied by causing an impregnated member containing the plating solution to face the conductive layer. Since the plating solution stays in the depression, a larger amount of plating solution is supplied than on the upper surface of the substrate, and the plating rate of the plating film in the depression increases. Consequently, the plating film can be preferentially formed in the depression such as a groove or hole.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: August 18, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuo Matsuda, Hisashi Kaneko, Katsuya Okumura
  • Patent number: 7554762
    Abstract: First and second shroud surfaces are defined along an imaginary cylinder coaxial to a recording disk. A shroud plate is located between the first and second shroud surfaces. Airflow flows outward along the surface of the rotating recording disk based on the centrifugal force. The shroud plate serves to establish the continuity of the first and second shroud surfaces. The first and second shroud surfaces and the shroud plate serve to reliably suppress turbulence of the airflow. Vibration of the recording disk is suppressed than ever. An inflow opening is located in a space between the first and second shroud surfaces. The rectifier plate is located downstream of the inflow opening. The rectifier plate serves to direct the airflow flowing along the first shroud surface to the inflow opening. A larger amount of airflow can be introduced into the inflow opening. A dust catcher receives airflow of a sufficient amount.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: June 30, 2009
    Assignee: Fujitsu Limited
    Inventors: Masaya Suwa, Hisashi Kaneko, Yoshiharu Matsuda, Keishi Shimizu
  • Publication number: 20090156002
    Abstract: A wafer is placed on a lower electrode disposed in a reaction chamber; process gas is introduced into the reaction chamber; a magnetic field is applied at a position spaced from a surface of the wafer to be processed; plasma is generated by applying a high-frequency voltage between the lower electrode and an upper electrode disposed to face the lower electrode; the magnetic field is removed after the plasma is stabilized; and the wafer is plasma-processed.
    Type: Application
    Filed: December 9, 2008
    Publication date: June 18, 2009
    Inventors: Keiji Fujita, Hisashi Kaneko
  • Patent number: 7531876
    Abstract: A semiconductor device which is compact and thin in size, low in resistance of a current path and parasitic inductance and excellent in reliability is provided. This semiconductor device comprises a semiconductor substrate, a first main electrode which is formed on a front surface of the semiconductor substrate, a second main electrode which is formed on a rear surface of the semiconductor substrate, and a conducting portion which is formed in a direction to pierce through the semiconductor substrate, wherein the second main electrode is extracted to the front surface of the semiconductor substrate via the conducting portion. And, the conducting portion is a through via which has a through hole formed through the semiconductor substrate in its thickness direction and a conductive portion which is formed in the through hole and connected to the second main electrode.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: May 12, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Omura, Kenji Takahashi, Chiaki Takubo, Hideo Aoki, Hideo Numata, Mie Matsuo, Hirokazu Ezawa, Susumu Harada, Hisashi Kaneko, Hiroshi Ikenoue, Kenichi Matsushita
  • Patent number: 7521352
    Abstract: A method for manufacturing a semiconductor device includes forming a copper anti-diffusion film on a copper trench wiring layer, and forming an opening portion in the copper anti-diffusion film by laser ablation, the opening portion being formed in a region corresponding to an alignment region used for lithography process for forming an aluminum wiring on the copper trench wiring layer.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: April 21, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideo Shinomiya, Jun Hirota, Mie Matsuo, Hisashi Kaneko
  • Publication number: 20090067086
    Abstract: A storage device includes plural recording media, a housing configured to accommodate the plural recording media, a plate that is fixed and extends round between two adjacent recording media in the housing, plural sliders each of which is mounted with a magnetic head that is configured to record information in or reproduce the information from a corresponding one of the plural recording media, and plural arms, each of which is mounted with one of the plural sliders only on a single surface, and configured to move the one of the plural sliders.
    Type: Application
    Filed: July 17, 2008
    Publication date: March 12, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Hisashi Kaneko, Yoshiharu Matsuda
  • Patent number: 7495866
    Abstract: A fixing member is spaced from a head actuator by a predetermined distance. A flexible printed circuit board extends at least from the head actuator to the fixing member. The flexible printed circuit board is superposed on the surface of the fixing member. A viscoelastic layer and a protecting layer are overlaid on the surface of the flexible printed circuit board. A clip clips all the fixing member, the flexible printed circuit board, the viscoelastic layer and the protecting layer together. When a head slider is positioned, the head actuator changes its attitude relative to a recording disk. The inertial force based on the rotation causes the first flexible printed circuit board to vibrate when the actuator block stops rotating. The viscoelastic layer serves to absorb this residual vibration of the first flexible printed circuit board. Vibration of the flexible printed circuit board can be suppressed.
    Type: Grant
    Filed: July 19, 2004
    Date of Patent: February 24, 2009
    Assignee: Fujitsu Limited
    Inventors: Mitsuhiro Izumi, Mitsuaki Yoshida, Hisashi Kaneko, Tsuneyori Ino, Yukihiro Komura, Shinji Fujimoto, Kei Funabashi