Patents by Inventor Hisashi Kato

Hisashi Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250110673
    Abstract: A mobile terminal device executes an OS including a printing system that supports a first search protocol and a printing function using a first printing method as a standard. If instructions for the use of the printing system included in the OS are provided by the user, the mobile terminal device receives a message conforming to the first search protocol from a printer that has been newly detected via the first search protocol. In a case where the detected printer has been selected, if the printer is determined not to conform to the first printing method based on the contents of the received message, the mobile terminal device activates a function for downloading a plug-in that supports the printer.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 3, 2025
    Inventor: Hisashi Kato
  • Publication number: 20250107095
    Abstract: A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.
    Type: Application
    Filed: December 11, 2024
    Publication date: March 27, 2025
    Applicant: Kioxia Corporation
    Inventors: Tadashi IGUCHI, Murato KAWAI, Toru MATSUDA, Hisashi KATO, Megumi ISHIDUKI
  • Patent number: 12261128
    Abstract: Semiconductor memory device includes: a first and second member each extending in a first direction in a boundary part between a first and second block region and arranged in the first direction; a support pillar arranged between the first and second member at the boundary part; conductive layers separated from one another and arranged in a third direction and split by the first and second member, and the support pillar into a first and second portion; and a memory pillar penetrating through the conductive layers. The support pillar includes a lower and upper pillar. A side face of the lower pillar and an extension of a side face of the upper pillar are displaced from each other in a plane based on a second and the third direction.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: March 25, 2025
    Assignee: Kioxia Corporation
    Inventors: Mitsunori Masaki, Hisashi Kato, Kazuhiro Nojima, Shoichi Miyazaki, Akira Yotsumoto, Kanako Shiga, Yu Hirotsu, Osamu Matsuura
  • Publication number: 20250096115
    Abstract: According to one embodiment, a semiconductor memory device includes first and second conductor layers, a first pillar, a first contact, and a source line drive circuit. The first pillar is passing through the second conductor layers. The first pillar includes a first semiconductor layer and a second insulator layer. The first semiconductor layer includes a side surface partially in contact with the first conductor layer. The first contact is passing through the second conductor layers. The first contact includes a third conductor layer and a third insulator layer. The third conductor layer includes a side surface partially in contact with the first conductor layer. The source line drive circuit is electrically coupled to the first conductor layer via the first contact.
    Type: Application
    Filed: November 27, 2024
    Publication date: March 20, 2025
    Applicant: KIOXIA CORPORATION
    Inventor: Hisashi KATO
  • Publication number: 20250070023
    Abstract: A semiconductor device includes a first chip including a first insulating layer; a second chip bonded to the first chip and including a second insulating layer; and a pad provided around a bonded surface between the first chip and the second chip. The pad includes a first metal layer including a first metal, a second metal layer disposed between the first metal layer and the first insulating layer, and a third metal layer disposed between the first metal layer and the second insulating layer. At least one of the second metal layer or the third metal layer include a second metal having oxidation energy lower than oxidation energy of the first metal. The first metal layer further includes the second metal.
    Type: Application
    Filed: August 19, 2024
    Publication date: February 27, 2025
    Applicant: Kioxia Corporation
    Inventors: Hisashi KATO, Masayoshi TAGAMI, Akira NAKAJIMA
  • Patent number: 12229458
    Abstract: A print processing system includes an image processing apparatus configured to execute print processing, and a client apparatus that includes a class driver configured to convert data as a target of the print processing into print data and to transmit a printing command for causing the image processing apparatus to execute the print processing by using a standard function to the image processing apparatus together with the print data, wherein the client apparatus includes an acquisition unit configured to acquire print setting information that specifies a print setting included in the image processing apparatus from the image processing apparatus via the class driver, a display unit configured to display a print setting screen based on the print setting information acquired by the acquisition unit, and a transmission unit configured to transmit the print setting information about a print setting selected by a user on the print setting screen.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: February 18, 2025
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hisashi Kato
  • Publication number: 20250031367
    Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.
    Type: Application
    Filed: October 3, 2024
    Publication date: January 23, 2025
    Applicant: KIOXIA CORPORATION
    Inventors: Takuya INATSUKA, Tadashi IGUCHI, Murato KAWAI, Hisashi KATO, Megumi ISHIDUKI
  • Publication number: 20250029956
    Abstract: A semiconductor memory device includes first and second chips that are bonded together. The first chip includes a stacked body in which memory cells are formed and first bonding electrodes, and the second chip includes second bonding electrodes. The first bonding electrodes and the second bonding electrodes are joined to each other to form joining electrodes. The stacked body includes an insulating layer that extends in a first direction to separate the stacked body in a second direction. The joining electrodes include first and second joining electrodes, the first joining electrodes being disposed adjacent to a first side of the insulating layer in a third direction, and the second joining electrodes being disposed adjacent to a second side of the insulating layer in the third direction. The first joining electrodes and the second joining electrodes are disposed in a staggered arrangement in the second direction and the third direction.
    Type: Application
    Filed: July 18, 2024
    Publication date: January 23, 2025
    Inventors: Yasunori IWASHITA, Hisashi KATO, Hiroaki ASHIDATE, Masayoshi TAGAMI
  • Patent number: 12197797
    Abstract: A mobile terminal device executes an OS including a printing system that supports a first search protocol and a printing function using a first printing method as a standard. If instructions for the use of the printing system included in the OS are provided by the user, the mobile terminal device receives a message conforming to the first search protocol from a printer that has been newly detected via the first search protocol. In a case where the detected printer has been selected, if the printer is determined not to conform to the first printing method based on the contents of the received message, the mobile terminal device activates a function for downloading a plug-in that supports the printer.
    Type: Grant
    Filed: August 1, 2023
    Date of Patent: January 14, 2025
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hisashi Kato
  • Patent number: 12199032
    Abstract: According to one embodiment, a semiconductor memory device includes first and second conductor layers, a first pillar, a first contact, and a source line drive circuit. The first pillar is passing through the second conductor layers. The first pillar includes a first semiconductor layer and a second insulator layer. The first semiconductor layer includes a side surface partially in contact with the first conductor layer. The first contact is passing through the second conductor layers. The first contact includes a third conductor layer and a third insulator layer. The third conductor layer includes a side surface partially in contact with the first conductor layer. The source line drive circuit is electrically coupled to the first conductor layer via the first contact.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: January 14, 2025
    Assignee: KIOXIA CORPORATION
    Inventor: Hisashi Kato
  • Patent number: 12200931
    Abstract: A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: January 14, 2025
    Assignee: Kioxia Corporation
    Inventors: Tadashi Iguchi, Murato Kawai, Toru Matsuda, Hisashi Kato, Megumi Ishiduki
  • Patent number: 12137559
    Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: November 5, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Takuya Inatsuka, Tadashi Iguchi, Murato Kawai, Hisashi Kato, Megumi Ishiduki
  • Publication number: 20240297146
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming, on a substrate, an active layer in which a dopant is implanted; forming a porous layer by making the active layer porous by an anodization treatment; forming a device layer including at least a part of a configuration of the semiconductor device above the porous layer; and cleaving the porous layer to remove the substrate.
    Type: Application
    Filed: February 27, 2024
    Publication date: September 5, 2024
    Applicant: Kioxia Corporation
    Inventors: Shota KONUMA, Hiroshi FUJITA, Hisashi KATO, Naomi YANAI
  • Patent number: 12040671
    Abstract: A motor coil substrate includes a flexible substrate, and coils formed on the flexible substrate. The flexible substrate is wound N times where N is 2 or larger, the coils are formed in a multiple of 3, the flexible substrate includes a first flexible substrate and a second flexible substrate extending from the first flexible substrate and wound around the first flexible substrate, the flexible substrate has a first end and a second end on an opposite side with respect to the first end such that the first flexible substrate has a first end of the flexible substrate, the second flexible substrate is positioned on an outer side of the first flexible substrate, and the coils are formed such that a coil or coils formed on the first flexible substrate partially overlap with a coil or coils formed on the second flexible substrate.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: July 16, 2024
    Assignee: IBIDEN CO., LTD.
    Inventors: Haruhiko Morita, Hitoshi Miwa, Shinobu Kato, Toshihiko Yokomaku, Hisashi Kato, Takahisa Hirasawa, Tetsuya Muraki, Takayuki Furuno
  • Patent number: 11973024
    Abstract: A semiconductor memory device according to an embodiment includes a substrate, conductive layers, pillars, and contacts. The substrate includes first and second areas, and block areas. The conductive layers are divided for each of the block areas. The conductive layers includes terraced portions. The contacts are respectively provided on the terraced portions for each of the block areas. The second area includes a first sub area and a second sub area. The first sub area includes a first stepped structure. The second sub area includes a second stepped structure and a first pattern. The first pattern is continuous with any one of the conductive layers. The first pattern is arranged between the first stepped structure and the second stepped structure.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: April 30, 2024
    Assignee: Kioxia Corporation
    Inventor: Hisashi Kato
  • Publication number: 20230422522
    Abstract: According to one embodiment, a semiconductor memory device includes a first chip and a second chip. The second chip is joined to the first chip at a first joining surface. The first chip includes a first memory cell array having a plurality of first memory cells. The first chip has a first wiring layer electrically connected to the first memory cell array. The second chip includes a second memory cell array that is electrically connected to the first wiring layer. The second memory cell array has a plurality of second memory cells. The second memory cell array shares the first wiring layer of the first chip with the first memory cell array. For example, the first wiring layer comprises bit lines which are shared by both the first and second memory cell arrays.
    Type: Application
    Filed: February 28, 2023
    Publication date: December 28, 2023
    Inventor: Hisashi KATO
  • Publication number: 20230397445
    Abstract: A semiconductor memory device includes a first chip, a second chip, a third chip, and a fourth chip. The second chip is bonded to the first chip. The third chip is bonded to the second chip on a side opposite to the first chip. The fourth chip is bonded to the third chip on a side opposite to the second chip. The third chip includes a first stacked body in which a plurality of first conductive layers are stacked in a first direction. The second chip includes a second stacked body in which a plurality of second conductive layers are stacked in the first direction. The first and second conductive layers each longitudinally extend in a second direction perpendicular to the first direction. The fourth chip includes a plurality of line patterns each extending in the second direction and aligned with each other in a third direction.
    Type: Application
    Filed: February 28, 2023
    Publication date: December 7, 2023
    Applicant: Kioxia Corporation
    Inventor: Hisashi KATO
  • Publication number: 20230395499
    Abstract: In one embodiment, a semiconductor device includes a first substrate, a first insulator provided on the first substrate, a first pad provided in the first insulator, a second insulator provided on the first insulator, and a second pad provided in the second insulator, disposed on the first pad, and being in contact with the first pad. The device further includes a third pad provided in the second insulator, and disposed above the second pad, a third insulator provided on the second insulator, and a fourth pad provided in the third insulator, disposed on the third pad, and being in contact with the third pad. Furthermore, a shape of the third or fourth pad is different from a shape of the first or second pad.
    Type: Application
    Filed: March 8, 2023
    Publication date: December 7, 2023
    Applicant: Kioxia Corporation
    Inventors: Hiroaki ASHIDATE, Hisashi KATO, Tomoyuki TAKEISHI
  • Publication number: 20230376257
    Abstract: A mobile terminal device executes an OS including a printing system that supports a first search protocol and a printing function using a first printing method as a standard. If instructions for the use of the printing system included in the OS are provided by the user, the mobile terminal device receives a message conforming to the first search protocol from a printer that has been newly detected via the first search protocol. In a case where the detected printer has been selected, if the printer is determined not to conform to the first printing method based on the contents of the received message, the mobile terminal device activates a function for downloading a plug-in that supports the printer.
    Type: Application
    Filed: August 1, 2023
    Publication date: November 23, 2023
    Inventor: Hisashi Kato
  • Patent number: 11756721
    Abstract: A planar transformer includes a coil substrate including a flexible substrate and multiple coils formed on the flexible substrate. The coil substrate is formed to have coil parts and coilless parts such that the coil parts have the coils and that the coilless parts do not have the coils, and the coil substrate is folded such that at least one of the coilless parts is sandwiched between two of the coil parts.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: September 12, 2023
    Assignee: IBIDEN CO., LTD.
    Inventors: Haruhiko Morita, Hitoshi Miwa, Shinobu Kato, Toshihiko Yokomaku, Hisashi Kato, Takahisa Hirasawa, Tetsuya Muraki, Takayuki Furuno