Patents by Inventor Hisashi Kato

Hisashi Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190074294
    Abstract: A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction. Ends of the first conductive layers and ends of the third conductive layers are formed in shapes of steps extending in the first direction and ends of the second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.
    Type: Application
    Filed: November 7, 2018
    Publication date: March 7, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Tadashi IGUCHI, Murato Kawai, Toru Matsuda, Hisashi Kato, Megumi Ishiduki
  • Publication number: 20190074745
    Abstract: A motor coil includes a magnet structure, and a laminated coil substrate formed on the magnet structure and including coil substrates and adhesive layers alternately laminated. The coil substrates are formed by folding a printed wiring board including a resin substrate, a first conductor layer formed on a first surface of the resin substrate and forming coils, and a second conductor layer formed on a second surface on the opposite side with respect to the first surface and forming coils, and the adhesive layers include an adhesive layer including a magnetic sheet.
    Type: Application
    Filed: September 7, 2018
    Publication date: March 7, 2019
    Applicant: IBIDEN CO. , LTD.
    Inventors: Haruhiko MORITA, Shinobu KATO, Hitoshi MIWA, Hisashi KATO, Toshihiko YOKOMAKU
  • Patent number: 10199386
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a first stacked body; a second stacked body being larger in number of stacked layers than the first stacked body, the second stacked body including a plurality of electrode layers separately stacked each other; a third stacked body being smaller in number of stacked layers than the first stacked body. The first stacked body includes a plurality of first layers separately stacked each other, and a plurality of second layers provided between the first layers. The third stacked body includes a third layer including a same material as the material of the first layers, and a fourth layer including a same material as the material of the second layers.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: February 5, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Terada, Hisashi Kato, Noriaki Koyama
  • Publication number: 20180374630
    Abstract: A coil includes a resin substrate, a first coil structure formed on a first surface of the resin substrate, a second coil structure formed on a second surface of the resin substrate on the opposite side with respect to the first surface such that the second coil structure is formed at a position corresponding to the first coil structure, a third coil structure formed on the second surface such that the third coil structure is positioned adjacent to the second coil structure, and a fourth coil structure formed on the first surface such that the fourth coil structure is formed at a position corresponding to the third coil structure. The resin substrate is folded such that the second coil structure and the third coil structure oppose each other.
    Type: Application
    Filed: June 27, 2018
    Publication date: December 27, 2018
    Applicant: IBIDEN CO., LTD.
    Inventors: Haruhiko MORITA, Shinobu Kato, Hitoshi Miwa, Hisashi Kato, Toshihiko Yokomaku
  • Patent number: 10147735
    Abstract: A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction. Ends of the first conductive layers and ends of the third conductive layers are formed in shapes of steps extending in the first direction and ends of the second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: December 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tadashi Iguchi, Murato Kawai, Toru Matsuda, Hisashi Kato, Megumi Ishiduki
  • Publication number: 20180210684
    Abstract: A mobile terminal device executes an OS including a printing system that supports a first search protocol and a printing function using a first printing method as a standard. If instructions for the use of the printing system included in the OS are provided by the user, the mobile terminal device receives a message conforming to the first search protocol from a printer that has been newly detected via the first search protocol. In a case where the detected printer has been selected, if the printer is determined not to conform to the first printing method based on the contents of the received message, the mobile terminal device activates a function for downloading a plug-in that supports the printer.
    Type: Application
    Filed: January 11, 2018
    Publication date: July 26, 2018
    Inventor: Hisashi Kato
  • Publication number: 20180182773
    Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.
    Type: Application
    Filed: February 23, 2018
    Publication date: June 28, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Takuya Inatsuka, Tadashi Iguchi, Murato Kawai, Hisashi Kato, Megumi Ishiduki
  • Patent number: 9966386
    Abstract: According to one embodiment, a semiconductor memory device includes first to third conductive layers extending along a first direction, and a memory portion. A portion of the second conductive layer is provided between the third conductive layer and a portion of the first conductive layer. The first conductive layer includes a first end portion crossing the first direction. The second conductive layer includes a second end portion crossing the first direction. The third conductive layer includes a third end portion crossing the first direction. A position in the first direction of a portion of the second end portion is between a position of the first end portion and a position of the third end portion. The position in the first direction of the portion of the second end portion is between a position of another portion of the second end portion and the position of the third end portion.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: May 8, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hisashi Kato, Hideki Inokuma, Naoki Yamamoto
  • Patent number: 9935118
    Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: April 3, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takuya Inatsuka, Tadashi Iguchi, Murato Kawai, Hisashi Kato, Megumi Ishiduki
  • Publication number: 20180090510
    Abstract: According to one embodiment, a semiconductor memory device includes first to third conductive layers extending along a first direction, and a memory portion. A portion of the second conductive layer is provided between the third conductive layer and a portion of the first conductive layer. The first conductive layer includes a first end portion crossing the first direction. The second conductive layer includes a second end portion crossing the first direction. The third conductive layer includes a third end portion crossing the first direction. A position in the first direction of a portion of the second end portion is between a position of the first end portion and a position of the third end portion. The position in the first direction of the portion of the second end portion is between a position of another portion of the second end portion and the position of the third end portion.
    Type: Application
    Filed: March 10, 2017
    Publication date: March 29, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Hisashi KATO, Hideki INOKUMA, Naoki YAMAMOTO
  • Publication number: 20180076211
    Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.
    Type: Application
    Filed: March 17, 2017
    Publication date: March 15, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Takuya INATSUKA, Tadashi IGUCHI, Murato KAWAI, Hisashi KATO, Megumi ISHIDUKI
  • Publication number: 20170352471
    Abstract: An inductor component includes a core base material, a magnetic body in the core, a first conductor pattern formed on primary surface of the core, a second conductor pattern formed on secondary surface of the core, and through-hole conductors formed in through holes through the core such that the conductors are connecting the first and second patterns. The first pattern, second pattern and conductors are positioned to form an inductor such that the magnetic body is positioned on inner side of the inductor, each conductor has a diameter k1, each pattern has conductor thickness in range of 50 ?m to 200 ?m and has line patterns each having width w1 and separated by line separation distance w2, and a ratio of cross-sectional area of each line pattern to cross-sectional area of each conductor along the diameter k1 in direction of the width w1 is in range of 0.8 to 2.0.
    Type: Application
    Filed: June 6, 2017
    Publication date: December 7, 2017
    Applicant: IBIDEN CO., LTD.
    Inventors: Yasuhiko Mano, Hiroaki Kodama, Hisashi Kato
  • Patent number: 9780104
    Abstract: An embodiment includes: a semiconductor substrate, a memory cell array region including a plurality of conductive layers connected to memory cells arranged in a stacking direction on the semiconductor substrate; a peripheral region including a transistor on the substrate; a plurality of first layers and second layers stacked alternately in the stacking direction, above the transistor; and a plurality of first contacts penetrating the plurality of first and second layers and connected to the transistor. The plurality of first layers and second layers are stacked alternately in the stacking direction, above the transistor disposed in the peripheral region. A plurality of contacts penetrating the plurality of first layers and second layers are connected to the transistor. Moreover, the first layer mainly contains a different material from the second layer.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: October 3, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akiko Nomachi, Hisashi Kato
  • Publication number: 20170251080
    Abstract: An information processing apparatus instructs a plurality of print plug-ins having at least a printer search function to search for a printer and displays, if the plurality of print plug-ins are instructed to perform the search, a first screen which includes (1) a printer detected by search processing performed by the plurality of print plug-ins instructed to perform the search and includes (2) an object for shifting to a second screen but does not include (3) a link to a download page of a print plug-in that is not installed, and displays, in response to an instruction given to the object in the first screen, the second screen which includes (3) the link to the download page of the print plug-in that is not installed.
    Type: Application
    Filed: February 21, 2017
    Publication date: August 31, 2017
    Inventor: Hisashi Kato
  • Patent number: 9612783
    Abstract: Information on a peripheral device in short distance wireless communication is obtained, it is determined whether the information contains an address of the peripheral device, and peripheral devices on a network is searched for if it is determined that the information does not contain the address of the peripheral device.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: April 4, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hisashi Kato
  • Patent number: 9601370
    Abstract: The memory cell array includes a memory string and a select transistor. The memory string includes plural memory cells connected in series, the memory string being formed to extend in a first direction as a lengthwise direction. The select transistor is connected to one end of the memory string. In the wiring section, a conductive layer and an interlayer insulating layer are laminated alternately to form plural layers. The conductive layer functions as a gate electrode of the memory cells and the select transistor. One select transistor includes plural conductive layers, and the plural conductive layers are connected in common by a common first contact. The plurality of the conductive layers and the first contact include a barrier metal formed in a periphery thereof. The plurality of the conductive layers and the first contact are in contact without the barrier metal therebetween at a boundary thereof.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: March 21, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hisashi Kato, Murato Kawai, Toru Matsuda, Takeshi Sonehara, Katsumi Iyanagi
  • Publication number: 20170077113
    Abstract: An embodiment includes: a semiconductor substrate, a memory cell array region including a plurality of conductive layers connected to memory cells arranged in a stacking direction on the semiconductor substrate; a peripheral region including a transistor on the substrate ; a plurality of first layers and second layers stacked alternately in the stacking direction, above the transistor; and a plurality of first contacts penetrating the plurality of first and second layers and connected to the transistor. The plurality of first layers and second layers are stacked alternately in the stacking direction, above the transistor disposed in the peripheral region. A plurality of contacts penetrating the plurality of first layers and second layers are connected to the transistor. Moreover, the first layer mainly contains a different material from the second layer.
    Type: Application
    Filed: March 16, 2016
    Publication date: March 16, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Akiko NOMACHI, Hisashi KATO
  • Publication number: 20170025423
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a first stacked body; a second stacked body being larger in number of stacked layers than the first stacked body, the second stacked body including a plurality of electrode layers separately stacked each other; a third stacked body being smaller in number of stacked layers than the first stacked body. The first stacked body includes a plurality of first layers separately stacked each other, and a plurality of second layers provided between the first layers. The third stacked body includes a third layer including a same material as the material of the first layers, and a fourth layer including a same material as the material of the second layers.
    Type: Application
    Filed: February 22, 2016
    Publication date: January 26, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takashi TERADA, Hisashi Kato, Noriaki Koyama
  • Publication number: 20160268298
    Abstract: A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction. Ends of the first conductive layers and ends of the third conductive layers are formed in shapes of steps extending in the first direction and ends of the second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.
    Type: Application
    Filed: September 10, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tadashi IGUCHI, Murato Kawai, Toru Matsuda, Hisashi Kato, Megumi Ishiduki
  • Publication number: 20160162227
    Abstract: An information processing apparatus manages whether each of a plurality of print plug-ins is in an enabled state or in a disabled state, the plurality of print plug-ins adding at least a search function to an operating system operating on the information processing apparatus, and, if a search for a printer is instructed and the plurality of print plug-ins includes a print plug-in in the disabled state, performs a search for a printer by a print plug-in in the enabled state, and displays a detection result and a setting screen for setting the print plug-in in the disabled state to the enabled state.
    Type: Application
    Filed: December 3, 2015
    Publication date: June 9, 2016
    Inventor: Hisashi Kato