Patents by Inventor Hisashi Ohtani

Hisashi Ohtani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120286280
    Abstract: A metal interconnection is located in the same layer as a source line and connected to the drain of a thin-film transistor. An interlayer insulating film is constituted of at least lower and upper insulating layers and formed between a conductive coating and the source line. According to one aspect of the invention, an auxiliary capacitor is formed by the metal interconnection and the conductive coating serving as both electrodes and at least the lower insulating layer serving as a dielectric. The auxiliary capacitor is formed in a region of the interlayer insulating film in which the upper insulating layer has been removed by etching.
    Type: Application
    Filed: May 18, 2012
    Publication date: November 15, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hisashi Ohtani, Yasushi Ogata, Yoshiharu Hirakata
  • Patent number: 8304350
    Abstract: A substrate processing apparatus includes a plurality of evacuable treatment chambers connected to one another via an evacuable common chamber, and the common chamber is provided with means for transporting a substrate between each treatment chamber. More specifically, a substrate processing apparatus includes a plurality of evacuable treatment chambers, at least one of said treatment chambers having a film formation function through a vapor phase reaction therein, at least one of said treatment chambers having an annealing function with light irradiation and at least one of said treatment chambers having a heating function therein. The apparatus also has a common chamber through which said plurality of evacuable treatment chambers are connected to one another, and a transportation means provided in said common chamber for transporting a substrate between each treatment chamber.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: November 6, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Hiroyuki Shimada, Mitsunori Sakama, Hisashi Abe, Satoshi Teramoto
  • Publication number: 20120261671
    Abstract: It is an object of the present invention to provide a technique to manufacture a highly reliable display device at a low cost with high yield. A display device according to the present invention includes a semiconductor layer including an impurity region of one conductivity type; a gate insulating layer, a gate electrode layer, and a wiring layer in contact with the impurity region of one conductivity type, which are provided over the semiconductor layer; a conductive layer which is formed over the gate insulating layer and in contact with the wiring layer; a first electrode layer in contact with the conductive layer; an electroluminescent layer provided over the first electrode layer; and a second electrode layer, where the wiring layer is electrically connected to the first electrode layer with the conductive layer interposed therebetween.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 18, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kengo AKIMOTO, Hisashi Ohtani, Misako Hirosue
  • Publication number: 20120211757
    Abstract: A semiconductor device includes TFTs designed in accordance with characteristics of circuits. In a first structure of the invention, the TFT is formed by using a crystalline silicon film made of a unique crystal structure body. The crystal structure body has a structure in which rod-like or flattened rod-like crystals grow in a direction parallel to each other. In a second structure of the invention, growth distances of lateral growth regions are made different from each other in accordance with channel lengths, of the TFTs. By this, characteristics of TFTs formed in one lateral growth region can be made as uniform as possible.
    Type: Application
    Filed: May 2, 2012
    Publication date: August 23, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Patent number: 8248551
    Abstract: A first insulating thin film having a large dielectric constant such as a silicon nitride film is formed so as to cover a source line and a metal wiring that is in the same layer as the source line. A second insulating film that is high in flatness is formed on the first insulating film. An opening is formed in the second insulating film by etching the second insulating film, to selectively expose the first insulating film. A conductive film to serve as a light-interruptive film is formed on the second insulating film and in the opening, whereby an auxiliary capacitor of the pixel is formed between the conductive film and the metal wiring with first the insulating film serving as a dielectric. The effective aperture ratio can be increased by forming the auxiliary capacitor in a selected region where the influences of alignment disorder of liquid crystal molecules, i.e., disclination, are large.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: August 21, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Yasushi Ogata
  • Publication number: 20120199986
    Abstract: A wiring line is electrically connected in parallel to an auxiliary wiring line via a plurality of contact holes. The contact holes are formed through an insulating film and arranged in vertical direction to the wiring line. Since the auxiliary wiring line is formed in the same layer as an electrode that constitutes a TFT, the electric resistance of the wiring line can be reduced effectively without increasing the number of manufacturing steps.
    Type: Application
    Filed: April 18, 2012
    Publication date: August 9, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Jun Koyama, Hisashi Ohtani, Yasushi Ogata, Shunpei Yamazaki
  • Patent number: 8237169
    Abstract: The object of the present invention is to form a low-concentration impurity region with good accuracy in a top gate type TFT. Phosphorus is added to a semiconductor layer by using a pattern made of a conductive film as a mask to form an N-type impurity region in a self-alignment manner. A positive photoresist is applied to a substrate so as to cover the pattern and then is exposed to light applied to the back of the substrate and then is developed, whereby a photoresist 110 is formed. The pattern is etched by using the photoresist pattern as an etching mask to form a gate electrode. A channel forming region, a source region, a drain region, and low-concentration impurity regions, are formed in the semiconductor layer in a self-alignment manner by using the gate electrode as a doping mask.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: August 7, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hisashi Ohtani
  • Patent number: 8222696
    Abstract: An active region, a source region, and a drain region are formed on a single crystal semiconductor substrate or a single crystal semiconductor thin film. Impurity regions called pinning regions are formed in striped form in the active region so as to reach both of the source region and the drain region. Regions interposed between the pinning regions serve as channel forming regions. A tunnel oxide film, a floating gate, a control gate, etc. are formed on the above structure. The impurity regions prevent a depletion layer from expanding from the source region toward the drain region.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: July 17, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Jun Koyama, Takeshi Fukunaga
  • Publication number: 20120175620
    Abstract: The inventors have anticipated that there is no problem in employing electron gun deposition as a method of forming a metallic layer on an EL layer of an active matrix light-emitting device because the TFT of the active matrix light-emitting device is disposed below the EL layer. However, since the TFT is extremely sensitive to ionized evaporated particles, the secondary electron, the reflecting electron, and so on generated by the electron gun, while little damage is observed on the EL layer, significant damage is found on the TFT when electron gun deposition is employed. The invention provides an active matrix light-emitting device having superior TFT characteristics (ON current, OFF to current, Vth, S-value, and so on), in which an organic compound layer and a metallic layer (cathode or anode) are formed by means of resistive heating having least influence to the TFT.
    Type: Application
    Filed: March 15, 2012
    Publication date: July 12, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Masakazu Murakami, Naomi Kawakami, Hisashi Ohtani
  • Patent number: 8218100
    Abstract: An conductive coating serves as a light shield film and is kept at a give voltage. A metal interconnection is located in the same layer as a source line and connected to the drain of a thin-film transistor. An interlayer insulating film is constituted of at least lower and upper insulating layers and formed between the conductive coating and the source line. According to one aspect of the invention, an auxiliary capacitor is formed by the metal interconnection and the conductive coating serving as both electrodes and at least the lower insulating layer film serving as a dielectric. The auxiliary capacitor is formed in a region of the interlayer insulating film in which the upper insulating layer has been removed by etching. According to another aspect of the invention, the conductive coating has a portion that is in contact with the lower insulating layer in a region where the conductive coating coextends with the metal interconnection.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: July 10, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Yasushi Ogata, Yoshiharu Hirakata
  • Patent number: 8212284
    Abstract: It is an object of the present invention to provide a technique to manufacture a highly reliable display device at a low cost with high yield. A display device according to the present invention includes a semiconductor layer including an impurity region of one conductivity type; a gate insulating layer, a gate electrode layer, and a wiring layer in contact with the impurity region of one conductivity type, which are provided over the semiconductor layer; a conductive layer which is formed over the gate insulating layer and in contact with the wiring layer; a first electrode layer in contact with the conductive layer; an electroluminescent layer provided over the first electrode layer; and a second electrode layer, where the wiring layer is electrically connected to the first electrode layer with the conductive layer interposed therebetween.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: July 3, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Hisashi Ohtani, Misako Hirosue
  • Publication number: 20120164801
    Abstract: A semiconductor device having a CMOS structure, wherein, in manufacturing a CMOS circuit, an impurity element which imparts p-type conductivity to the active layer of the p-channel type semiconductor device is added before forming the gate insulating film. Then, by applying thermal oxidation treatment to the active layer, the impurity element is subjected to redistribution, and the concentration of the impurity element in the principal surface of the active layer is minimized. The precise control of threshold voltage is enabled by the impurity element that is present in a trace quantity.
    Type: Application
    Filed: March 5, 2012
    Publication date: June 28, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Takeshi Fukunaga
  • Patent number: 8193533
    Abstract: To provide a semiconductor device having a function equivalent to that of IGFET, an activation layer is formed by a crystal silicon film crystallized by using a catalyst element helping promote crystallization and a heating treatment is carried out in an atmosphere including a halogen element by which the catalyst element is removed, the activation layer processed by such steps is constituted by a peculiar crystal structure and according to the crystal structure, a rate of incommensurate bonds in respect of all of bonds at grain boundaries is 5% or less (preferably, 3% or less).
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: June 5, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Publication number: 20120108049
    Abstract: There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. A catalytic element for facilitating crystallization of an amorphous semiconductor thin film is added to the amorphous semiconductor thin film, and a heat treatment is carried out to obtain a crystalline semiconductor thin film. After the crystalline semiconductor thin film is irradiated with ultraviolet light or infrared light, a heat treatment at a temperature of 900 to 1200° C. is carried out in a reducing atmosphere. The surface of the crystalline semiconductor thin film is extremely flattened through this step, defects in crystal grains and crystal grain boundaries disappear, and the single crystal semiconductor thin film or substantially single crystal semiconductor thin film is obtained.
    Type: Application
    Filed: December 28, 2011
    Publication date: May 3, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hisashi OHTANI, Tamae TAKANO
  • Patent number: 8168975
    Abstract: A wiring line is electrically connected in parallel to an auxiliary wiring line via a plurality of contact holes. The contact holes are formed through an insulating film and arranged in vertical direction to the wiring line. Since the auxiliary wiring line is formed in the same layer as an electrode that constitutes a TFT, the electric resistance of the wiring line can be reduced effectively without increasing the number of manufacturing steps.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: May 1, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Hisashi Ohtani, Yasushi Ogata, Shunpei Yamazaki
  • Patent number: 8154676
    Abstract: An conductive coating serves as a light shield film and is kept at a give voltage. A metal interconnection is located in the same layer as a source line and connected to the drain of a thin-film transistor. An interlayer insulating film is constituted of at least lower and upper insulating layers and formed between the conductive coating and the source line. According to one aspect of the invention, an auxiliary capacitor is formed by the metal interconnection and the conductive coating serving as both electrodes and at least the lower insulating layer film serving as a dielectric. The auxiliary capacitor is formed in a region of the interlayer insulating film in which the upper insulating layer has been removed by etching. According to another aspect of the invention, the conductive coating has a portion that is in contact with the lower insulating layer in a region where the conductive coating coextends with the metal interconnection.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: April 10, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Yasushi Ogata, Yoshiharu Hirakata
  • Patent number: 8143625
    Abstract: There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. A catalytic element for facilitating crystallization of an amorphous semiconductor thin film is added to the amorphous semiconductor thin film, and a heat treatment is carried out to obtain a crystalline semiconductor thin film. After the crystalline semiconductor thin film is irradiated with ultraviolet light or infrared light, a heat treatment at a temperature of 900 to 1200° C. is carried out in a reducing atmosphere. The surface of the crystalline semiconductor thin film is extremely flattened through this step, defects in crystal grains and crystal grain boundaries disappear, and the single crystal semiconductor thin film or substantially single crystal semiconductor thin film is obtained.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: March 27, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Tamae Takano
  • Patent number: 8138670
    Abstract: The inventors have anticipated that there is no problem in employing electron gun deposition as a method of forming a metallic layer on an EL layer of an active matrix light-emitting device because the TFT of the active matrix light-emitting device is disposed below the EL layer. However, since the TFT is extremely sensitive to ionized evaporated particles, the secondary electron, the reflecting electron, and so on generated by the electron gun, while little damage is observed on the EL layer, significant damage is found on the TFT when electron gun deposition is employed. The invention provides an active matrix light-emitting device having superior TFT characteristics (ON current, OFF to current, Vth, S-value, and so on), in which an organic compound layer and a metallic layer (cathode or anode) are formed by means of resistive heating having least influence to the TFT.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: March 20, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masakazu Murakami, Naomi Kawakami, Hisashi Ohtani
  • Patent number: RE43450
    Abstract: An object of the present invention is to provide a technology of reducing a nickel element in the silicon film which is crystallized by using nickel. An extremely small amount of nickel is introduced into an amorphous silicon film which is formed on the glass substrate. Then this amorphous silicon film is crystallized by heating. At this time, the nickel element remains in the crystallized silicon film. Then an amorphous silicon film is formed on the surface of the silicon film crystallized with the action of nickel. Then the amorphous silicon film is further heat treated. By carrying out this heat treatment, the nickel element is dispersed from the crystallized silicon film into the amorphous silicon film with the result that the nickel density in the crystallized silicon film is lowered.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: June 5, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Akiharu Miyanaga, Satoshi Teramoto
  • Patent number: RE43782
    Abstract: A wiring line to which a high-frequency signal is applied is electrically connected in parallel to an auxiliary wiring line via a plurality of contact holes. The contact holes are formed through an interlayer insulating film and arranged in vertical direction to the wiring line. Since the auxiliary wiring line is formed in the same layer as an electrode that constitutes a TFT, the electric resistance of the wiring line can be reduced effectively and waveform rounding of an applied high-frequency signal can be reduced without increasing the number of manufacturing steps.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: November 6, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Hisashi Ohtani, Yasushi Ogata, Shunpei Yamazaki