Patents by Inventor Hisashi Ohtani

Hisashi Ohtani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8129232
    Abstract: A semiconductor device having a CMOS structure, wherein, in manufacturing a CMOS circuit, an impurity element which imparts p-type conductivity to the active layer of the p-channel type semiconductor device is added before forming the gate insulating film. Then, by applying thermal oxidation treatment to the active layer, the impurity element is subjected to redistribution, and the concentration of the impurity element in the principal surface of the active layer is minimized. The precise control of threshold voltage is enabled by the impurity element that is present in a trace quantity.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: March 6, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Takeshi Fukunaga
  • Publication number: 20120034766
    Abstract: A process for fabricating a highly stable and reliable semiconductor, comprising: coating the surface of an amorphous silicon film with a solution containing a catalyst element capable of accelerating the crystallization of the amorphous silicon film, and heat treating the amorphous silicon film thereafter to crystallize the film.
    Type: Application
    Filed: August 15, 2011
    Publication date: February 9, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hisashi OHTANI, Akiharu MIYANAGA, Takeshi FUKUNAGA, Hongyong ZHANG
  • Publication number: 20120019739
    Abstract: There is disclosed an active matrix reflective liquid crystal display panel on which an active matrix circuit is integrated with peripheral driver circuits. Metal lines in the peripheral driver circuits are formed simultaneously with pixel electrodes. Thus, neither the process sequence nor the structure is complicated.
    Type: Application
    Filed: September 28, 2011
    Publication date: January 26, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hisashi OHTANI, Jun KOYAMA, Satoshi TERAMOTO
  • Publication number: 20120012852
    Abstract: The object of the present invention is to form a low-concentration impurity region with good accuracy in a top gate type TFT. Phosphorus is added to a semiconductor layer by using a pattern made of a conductive film as a mask to form an N-type impurity region in a self-alignment manner. A positive photoresist is applied to a substrate so as to cover the pattern and then is exposed to light applied to the back of the substrate and then is developed, whereby a photoresist 110 is formed. The pattern is etched by using the photoresist pattern as an etching mask to form a gate electrode. A channel forming region, a source region, a drain region, and low-concentration impurity regions, are formed in the semiconductor layer in a self-alignment manner by using the gate electrode as a doping mask.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 19, 2012
    Inventor: Hisashi Ohtani
  • Publication number: 20110262117
    Abstract: An object is to provide a method of activating impurity elements added to a semiconductor film, and a method of gettering, in a process of manufacturing a semiconductor device using a substrate having a low resistance to heat, such as glass, without changing the shape of the substrate, by using a short time heat treatment process. Another object is to provide a heat treatment apparatus that makes this type of heat treatment process possible. A unit for supplying a gas from the upstream side of a reaction chamber, a unit for heating the gas in the upstream side of the reaction chamber, a unit for holding a substrate to be processed in the downstream side of the reaction chamber, and a unit for circulating the gas from the downstream side of the reaction chamber to the upstream side are prepared. The amount of electric power used in heating the gas can be economized by circulating the gas used to heat the substrate to be processed.
    Type: Application
    Filed: July 1, 2011
    Publication date: October 27, 2011
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Yasuyuki Arai
  • Publication number: 20110254009
    Abstract: The object is to pattern extremely fine integrated circuits by forming fine contact holes. The dry etching method is employed to form contact holes to pattern a wiring (114), using a mask made of metallic film (112) and an organic material as an inter-layer insulating film (111) for covering switching elements and each of the wirings.
    Type: Application
    Filed: June 27, 2011
    Publication date: October 20, 2011
    Inventors: Hisashi Ohtani, Misako Nakazawa, Satoshi Murakami, Etsuko Fujimoto
  • Patent number: 8031284
    Abstract: There is disclosed an active matrix reflective liquid crystal display panel on which an active matrix circuit is integrated with peripheral driver circuits. Metal lines in the peripheral driver circuits are formed simultaneously with pixel electrodes. Thus, neither the process sequence nor the structure is complicated.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: October 4, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Jun Koyama, Satoshi Teramoto
  • Patent number: 8030658
    Abstract: The object of the present invention is to form a low-concentration impurity region with good accuracy in a top gate type TFT. Phosphorus is added to a semiconductor layer by using a pattern made of a conductive film as a mask to form an N-type impurity region in a self-alignment manner. A positive photoresist is applied to a substrate so as to cover the pattern and then is exposed to light applied to the back of the substrate and then is developed, whereby a photoresist 110 is formed. The pattern is etched by using the photoresist pattern as an etching mask to form a gate electrode. A channel forming region, a source region, a drain region, and low-concentration impurity regions, are formed in the semiconductor layer in a self-alignment manner by using the gate electrode as a doping mask.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: October 4, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hisashi Ohtani
  • Publication number: 20110233556
    Abstract: The present invention provides a semiconductor device which is not easily damaged by external local pressure. The present invention further provides a method for manufacturing a highly-reliable semiconductor device, which is not destructed by external local pressure, with a high yield. A structure body, in which high-strength fiber of an organic compound or an inorganic compound is impregnated with an organic resin, is provided over an element layer having a semiconductor element formed using a non-single crystal semiconductor layer, and heating and pressure bonding are performed, whereby a semiconductor device is manufactured, to which the element layer and the structure body in which the high-strength fiber of an organic compound or an inorganic compound is impregnated with the organic resin are firmly fixed together.
    Type: Application
    Filed: June 10, 2011
    Publication date: September 29, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Eiji SUGIYAMA, Yoshitaka DOZEN, Hisashi OHTANI, Takuya TSURUME
  • Publication number: 20110215327
    Abstract: A first insulating thin film having a large dielectric constant such as a silicon nitride film is formed so as to cover a source line and a metal wiring that is in the same layer as the source line. A second insulating film that is high in flatness is formed on the first insulating film. An opening is formed in the second insulating film by etching the second insulating film, to selectively expose the first insulating film. A conductive film to serve as a light-interruptive film is formed on the second insulating film and in the opening, whereby an auxiliary capacitor of the pixel is formed between the conductive film and the metal wiring with first the insulating film serving as a dielectric. The effective aperture ratio can be increased by forming the auxiliary capacitor in a selected region where the influences of alignment disorder of liquid crystal molecules, i.e., disclination, are large.
    Type: Application
    Filed: May 19, 2011
    Publication date: September 8, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hisashi OHTANI, Yasushi OGATA
  • Patent number: 8012529
    Abstract: According to the invention, an insulating or semi-insulating barrier layer which has a thickness where a tunnel current can flow through is provided between a hole injection electrode and an organic compound layer with hole transport characteristics (a hole injection layer or a hole transport layer). Specifically, a thin insulating or semi-insulating barrier layer which contains silicon or silicon oxide; silicon or silicon oxide and a light transmitting conductive oxide material; or silicon or silicon oxide, a light transmitting conductive oxide material, and carbon may be provided between a light transmitting conductive oxide film formed of a light transmitting conductive oxide material, such as ITO and a hole injection layer containing an organic compound.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: September 6, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Masakazu Murakami, Koji Moriya, Yoshiaki Oikawa, Taketomi Asami, Hisashi Ohtani
  • Patent number: 7998844
    Abstract: A process for fabricating a highly stable and reliable semiconductor, comprising: coating the surface of an amorphous silicon film with a solution containing a catalyst element capable of accelerating the crystallization of the amorphous silicon film, and heat treating the amorphous silicon film thereafter to crystallize the film.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: August 16, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Akiharu Miyanaga, Takeshi Fukunaga, Hongyong Zhang
  • Patent number: 7993992
    Abstract: There is disclosed a method of fabricating TFTs having reduced interconnect resistance by having improved contacts to source/drain regions. A silicide layer is formed in intimate contact with the source/drain regions. The remaining metallization layer is selectively etched to form a contact pad or conductive interconnects.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: August 9, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Etsuko Fujimoto
  • Publication number: 20110186949
    Abstract: A semiconductor device capable of wireless communication, which has high reliability in terms of resistance to external force, in particular, pressing force and can prevent electrostatic discharge in an integrated circuit without preventing reception of an electric wave. The semiconductor device includes an on-chip antenna connected to the integrated circuit and a booster antenna which transmits a signal or power included in a received electric wave to the on-chip antenna without contact. In the semiconductor device, the integrated circuit and the on-chip antenna are interposed between a pair of structure bodies formed by impregnating a fiber body with a resin. One of the structure bodies is provided between the on-chip antenna and the booster antenna. A conductive film having a surface resistance value of approximately 106 to 1014 ?/cm2 is formed on at least one surface of each structure body.
    Type: Application
    Filed: April 12, 2011
    Publication date: August 4, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Kiyoshi KATO, Takaaki KOEN, Yuto YAKUBO, Makoto YANAGISAWA, Hisashi OHTANI, Eiji SUGIYAMA, Nozomi HORIKOSHI
  • Patent number: 7974524
    Abstract: An object is to provide a method of activating impurity elements added to a semiconductor film, and a method of gettering, in a process of manufacturing a semiconductor device using a substrate having a low resistance to heat, such as glass, without changing the shape of the substrate, by using a short time heat treatment process. Another object is to provide a heat treatment apparatus that makes this type of heat treatment process possible. A unit for supplying a gas from the upstream side of a reaction chamber, a unit for heating the gas in the upstream side of the reaction chamber, a unit for holding a substrate to be processed in the downstream side of the reaction chamber, and a unit for circulating the gas from the downstream side of the reaction chamber to the upstream side are prepared. The amount of electric power used in heating the gas can be economized by circulating the gas used to heat the substrate to be processed.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: July 5, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Yasuyuki Arai
  • Patent number: 7968427
    Abstract: The present invention provides a semiconductor device which is not easily damaged by external local pressure. The present invention further provides a method for manufacturing a highly-reliable semiconductor device, which is not destructed by external local pressure, with a high yield. A structure body, in which high-strength fiber of an organic compound or an inorganic compound is impregnated with an organic resin, is provided over an element layer having a semiconductor element formed using a non-single crystal semiconductor layer, and heating and pressure bonding are performed, whereby a semiconductor device is manufactured, to which the element layer and the structure body in which the high-strength fiber of an organic compound or an inorganic compound is impregnated with the organic resin are firmly fixed together.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: June 28, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Eiji Sugiyama, Yoshitaka Dozen, Hisashi Ohtani, Takuya Tsurume
  • Publication number: 20110148285
    Abstract: It is an object of the invention to provide a light emitting device in which burden on a light emitting element having low luminous efficiency is relieved, and the deterioration of a light emitting element, the reduction in color reproduction due to the deteriorated light emitting element, and increase in electric power consumption can be suppressed. A light emitting device according to the invention has light emitting elements each of which emits one of colors corresponding to three primary colors. Further, one feature of the light emitting device according to the invention has a light emitting element which emits a neutral color. The light emitting device according to the invention has a structure in which a plurality of pixels having light emitting elements each of which emits one of colors corresponding to three primary colors, and a light emitting element which emits a neutral color as one group, are arranged.
    Type: Application
    Filed: February 25, 2011
    Publication date: June 23, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Hisashi Ohtani
  • Publication number: 20110147758
    Abstract: An conductive coating serves as a light shield film and is kept at a give voltage. A metal interconnection is located in the same layer as a source line and connected to the drain of a thin-film transistor. An interlayer insulating film is constituted of at least lower and upper insulating layers and formed between the conductive coating and the source line. According to one aspect of the invention, an auxiliary capacitor is formed by the metal interconnection and the conductive coating serving as both electrodes and at least the lower insulating layer film serving as a dielectric. The auxiliary capacitor is formed in a region of the interlayer insulating film in which the upper insulating layer has been removed by etching. According to another aspect of the invention, the conductive coating has a portion that is in contact with the lower insulating layer in a region where the conductive coating coextends with the metal interconnection.
    Type: Application
    Filed: February 25, 2011
    Publication date: June 23, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hisashi Ohtani, Yasushi Ogata, Yoshiharu Hirakata
  • Patent number: 7948571
    Abstract: A first insulating thin film having a large dielectric constant such as a silicon nitride film is formed so as to cover a source line and a metal wiring that is in the same layer as the source line. A second insulating film that is high in flatness is formed on the first insulating film. An opening is formed in the second insulating film by etching the second insulating film, to selectively expose the first insulating film. A conductive film to serve as a light-interruptive film is formed on the second insulating film and in the opening, whereby an auxiliary capacitor of the pixel is formed between the conductive film and the metal wiring with first the insulating film serving as a dielectric. The effective aperture ratio can be increased by forming the auxiliary capacitor in a selected region where the influences of alignment disorder of liquid crystal molecules, i.e., disclination, are large.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: May 24, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Yasushi Ogata
  • Publication number: 20110114936
    Abstract: It is an object of the present invention to provide a technique to manufacture a highly reliable display device at a low cost with high yield. A display device according to the present invention includes a semiconductor layer including an impurity region of one conductivity type; a gate insulating layer, a gate electrode layer, and a wiring layer in contact with the impurity region of one conductivity type, which are provided over the semiconductor layer; a conductive layer which is formed over the gate insulating layer and in contact with the wiring layer; a first electrode layer in contact with the conductive layer; an electroluminescent layer provided over the first electrode layer; and a second electrode layer, where the wiring layer is electrically connected to the first electrode layer with the conductive layer interposed therebetween.
    Type: Application
    Filed: January 20, 2011
    Publication date: May 19, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kengo AKIMOTO, Hisashi OHTANI, Misako HIROSUE