Abstract: A motor driver device includes: a detector that detects a polarity inversion timing of a current flowing through a coil of a predetermined phase of a motor; a drive control signal generator that generates a pulse-width-modulated or pulse-density-modulated drive control signal for each phase based on the detection result; and a drive voltage supply that supplies a drive voltage corresponding to the drive control signal to a corresponding coil, wherein the drive control signal generator includes a prediction processor configured to set a detection prediction interval based on two or more previously detected polarity inversion timings, and executes a frequency variable control to set a variable target frequency to be higher in the detection prediction interval than outside the detection prediction interval, the variable target frequency being a frequency of the pulse-width-modulated drive control signal or a reciprocal of a minimum pulse width of the pulse-density-modulated drive control signal.

Abstract: A bridge output circuit includes: a voltage-controlled first transistor provided between a first power supply terminal and an output terminal; a voltage-controlled second transistor provided between the output terminal and a second power supply terminal having a potential lower than the potential of the first power supply terminal; a first OFF detection circuit detecting whether the first transistor is in an OFF state based on a gate voltage of the first transistor; a second OFF detection circuit detecting whether the second transistor is in an OFF state based on a gate voltage of the second transistor; and an output control circuit performing a first source transition operation of turning off the second transistor and then turning on the first transistor, and then performing a second source transition operation of turning off the first transistor and then turning on the second transistor.

Abstract: Disclosed herein is an amplification circuit that outputs an output signal formed by amplifying a differential signal between a first input terminal and a second input terminal using an operating amplifier and a plurality of resistors, the amplification circuit including an adjustment circuit configured to adjust a frequency property of the output signal for an in-phase alternating current signal input between the first input terminal and the second input terminal. The adjustment circuit is connected to one input terminal of the first input terminal and the second input terminal through one or more resistors, the adjustment circuit includes a capacitor part whose capacitance is set to be variable, and the adjustment is realized through variable setting of the capacitance of the capacitor part.

Abstract: A motor driving circuit for driving a motor, includes: a detecting circuit configured to detect a detection signal indicative of a current state of the motor; a command value generating unit configured to generate a command value indicative of a target state of the motor; an error amplifier configured to generate an error signal by amplifying an error between the detection signal and the command value; a pulse width modulator configured to generate a pulse signal; and an output circuit. The command value generating unit is configured to provide a variation to the command value.

Abstract: A variable gain amplifier includes: a first input terminal, a second input terminal and an output terminal; an operational amplifier; a first resistor interposed between the first input terminal and an inverted input terminal of the operational amplifier; second and third resistors interposed between the inverted input terminal and the output terminal; and a fourth variable resistor having a first terminal connected to a node between the second resistor and the third resistor and a second terminal connected to the non-inverted input terminal, wherein the fourth variable resistor includes a resistance pass including a resistor and a switch.

Abstract: A bridge output circuit includes an output terminal, a high side transistor, a low side transistor, a high side driver for controlling a gate voltage of the high side transistor, a low side driver for controlling a gate voltage of the low side transistor, and a controller for controlling the high side and low side drivers. The low side driver includes a first current source, a second current source, and a first assist circuit. The controller is configured to control the turning-on and turning-off states of the first current source, the second current source and the first assist circuit.

Abstract: A class-AB amplifier has upper side and lower side transistors, a linear driver, upper side and lower side idlers, upper side and lower side detection current generators, and an off driver. The upper side and lower side idlers bias upper side and lower side gate voltages by generating upper side and lower side bias currents so as to turn on the upper side and the lower side transistors at the same time in the crossover region between an input voltage and a reference voltage respectively. The upper side detection current generator and the lower side detection current generator generates upper side and lower side detection currents in accordance with upper side and lower side bias currents respectively.

Abstract: A class-AB amplifier has upper side and lower side transistors, a linear driver, upper side and lower side idlers, upper side and lower side detection current generators, and an off driver. The upper side and lower side idlers bias upper side and lower side gate voltages by generating upper side and lower side bias currents so as to turn on the upper side and the lower side transistors at the same time in the crossover region between an input voltage and a reference voltage respectively. The upper side detection current generator and the lower side detection current generator generates upper side and lower side detection currents in accordance with upper side and lower side bias currents respectively.

Abstract: A low-side off-detection signal compares the gate signal of a low-side transistor with a predetermined first level to generate a low-side off-detection signal indicating that the low-side transistor is off. The low-side detection transistor is of the same type as the low-side transistor, with the source connected to the ground terminal, and the gate receiving the low-side transistor gate signal. A first resistor is arranged between the drain of the low-side detection transistor and the power supply terminal. A first bypass circuit is arranged in parallel with the first resistor, and is configured to switch to the conduction state when a control signal is a level which instructs the low-side transistor to switch off, and to switch to the cut-off state when the control signal level instructs the low-side transistor to switch on. The drain signal of the low-side detection transistor is output as the low-side off-detection signal.

Abstract: A motor driving circuit for driving a motor, includes: a detecting circuit configured to detect a detection signal indicative of a current state of the motor; a command value generating unit configured to generate a command value indicative of a target state of the motor; an error amplifier configured to generate an error signal by amplifying an error between the detection signal and the command value; a pulse width modulator configured to generate a pulse signal; and an output circuit. The command value generating unit is configured to provide a variation to the command value.

Abstract: A bridge output circuit includes an output terminal, a high side transistor, a low side transistor, a high side driver for controlling a gate voltage of the high side transistor, a low side driver for controlling a gate voltage of the low side transistor, and a controller for controlling the high side and low side drivers. The low side driver includes a first current source, a second current source, and a first assist circuit. The controller is configured to control the turning-on and turning-off states of the first current source, the second current source and the first assist circuit.

Abstract: A variable gain amplifier includes: a first input terminal, a second input terminal and an output terminal; an operational amplifier; a first resistor interposed between the first input terminal and an inverted input terminal of the operational amplifier; second and third resistors interposed between the inverted input terminal and the output terminal; and a fourth variable resistor having a first terminal connected to a node between the second resistor and the third resistor and a second terminal connected to the non-inverted input terminal, wherein the fourth variable resistor includes a resistance pass including a resistor and a switch.

Abstract: With an oscillator circuit with a frequency sweep function, a first counter counts a reference clock for a number of counts that corresponds to a digital first setting signal, and generates a first count completion signal which is asserted on completion of the count. A D/A converter converts a digital second setting signal into an analog control voltage. A VCO oscillates with a frequency according to the control voltage. When the first count completion signal is asserted, the VCO is reset. An output combining unit receives the output signal of the VCO, generates the output signal of the oscillator circuit, and generates the first setting signal and the second setting signal.

Abstract: Multiple pads are provided to a semiconductor chip of a semiconductor device. A first pad is arranged on a path for a first signal set to a voltage that corresponds to a first level in the active state. The first signal is input to the semiconductor chip from outside the semiconductor device, or is output to outside the semiconductor device from the semiconductor chip. A second pad is provided in order to receive a setting voltage. A first pin is connected to a first pad via a connection member, and receives the first signal from outside the semiconductor device, or from the semiconductor chip via the first pad. A second pin receives, from outside, a second signal set to a voltage that corresponds to the first level or a second level which is the complement of the first level.

Abstract: A low-side off-detection signal compares the gate signal of a low-side transistor with a predetermined first level to generate a low-side off-detection signal indicating that the low-side transistor is off. The low-side detection transistor is of the same type as the low-side transistor, with the source connected to the ground terminal, and the gate receiving the low-side transistor gate signal. A first resistor is arranged between the drain of the low-side detection transistor and the power supply terminal. A first bypass circuit is arranged in parallel with the first resistor, and is configured to switch to the conduction state when a control signal is a level which instructs the low-side transistor to switch off, and to switch to the cut-off state when the control signal level instructs the low-side transistor to switch on. The drain signal of the low-side detection transistor is output as the low-side off-detection signal.

Abstract: A power transistor is arranged between an output terminal and a power supply terminal. A pre-driver includes a high-side transistor and a low-side transistor connected in series between the power supply terminal and a second terminal, and the ON/OFF operations of which are controlled in a complementary manner according to a control signal. The electric potential at a connection node between the two transistors is output to a control terminal of the power transistor. A constant voltage circuit stabilizes the second terminal to a predetermined voltage. An output transistor for the constant voltage circuit is provided between the second terminal and the ground terminal. A differential amplifier adjusts the voltage applied to the control terminal of the output transistor such that the electric potential at the second terminal approaches a predetermined target value. A feedback capacitor is provided between the second terminal and the control terminal of the output transistor.

Abstract: When the bit number of an error signal ERR2 is n and the magnitude of the error signal ERR2 is “a” (a is an integer) in decimal notation, a pulse-width modulator generates a PWM signal Spwm as a set of k (k is an integer of 2 or more) continuous sub-pulses. Further, the pulse-width modulator generates k sub-pulses in such a manner that the average value of the duty ratios of the sub-pulses becomes approximately a/2n.

Abstract: With an oscillator circuit with a frequency sweep function, a first counter counts a reference clock for a number of counts that corresponds to a digital first setting signal, and generates a first count completion signal which is asserted on completion of the count. A D/A converter converts a digital second setting signal into an analog control voltage. A VCO oscillates with a frequency according to the control voltage. When the first count completion signal is asserted, the VCO is reset. An output combining unit receives the output signal of the VCO, generates the output signal of the oscillator circuit, and generates the first setting signal and the second setting signal.

Abstract: At an occasion of a level transition when a second periodic voltage becomes equal to a main reference voltage a first periodic voltage generating circuit starts a first monotonically changing time-period in which a voltage value of a first periodic voltage increases monotonically from 0, which is an initial value, towards a voltage value of the main reference voltage. At an occasion of a level transition of a first main switching signal when the first periodic voltage becomes equal to the main reference voltage, a second periodic voltage generating circuit starts a second monotonically changing time-period in which a voltage value of the second periodic voltage increases monotonically from 0, which is an initial value, towards a voltage value of the main reference voltage.

Abstract: Multiple pads are provided to a semiconductor chip of a semiconductor device. A first pad is arranged on a path for a first signal set to a voltage that corresponds to a first level in the active state. The first signal is input to the semiconductor chip from outside the semiconductor device, or is output to outside the semiconductor device from the semiconductor chip. A second pad is provided in order to receive a setting voltage. A first pin is connected to a first pad via a connection member, and receives the first signal from outside the semiconductor device, or from the semiconductor chip via the first pad. A second pin receives, from outside, a second signal set to a voltage that corresponds to the first level or a second level which is the complement of the first level.