Patents by Inventor Hisashi Yoshida
Hisashi Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9397167Abstract: A nitride semiconductor wafer includes a silicon substrate, a stacked multilayer unit, a silicon-containing unit, and an upper layer unit. The silicon substrate has a major surface. The stacked multilayer unit is provided on the major surface. The stacked multilayer unit includes N number of buffer layers. The buffer layers include an i-th buffer layer, and an (i+1)-th buffer layer provided on the i-th buffer layer. The i-th buffer layer has an i-th lattice length Wi in a first direction parallel to the major surface. The (i+1)-th buffer layer has an (i+1)-th lattice length W(i+1) in the first direction. A relation that (W(i+1)?Wi)/Wi?0.008 is satisfied for all the buffer layers. The silicon-containing unit is provided on the stacked multilayer unit. The upper layer unit is provided on the silicon-containing unit.Type: GrantFiled: December 28, 2012Date of Patent: July 19, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hisashi Yoshida, Toshiki Hikosaka, Yoshiyuki Harada, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 9391145Abstract: According to one embodiment, a nitride semiconductor element includes a functional layer and a stacked body. The stacked body includes a GaN intermediate layer, a low Al composition layer, a high Al composition layer, and a first Si-containing layer. The low Al composition layer includes a nitride semiconductor having a first Al composition ratio. The low Al composition layer is provided between the GaN intermediate layer and the functional layer. The high Al composition layer includes a nitride semiconductor having a second Al composition ratio. The high Al composition layer is provided between the GaN intermediate layer and the low Al composition layer. The second Al composition ratio is higher than the first Al composition ratio. The first Si-containing layer is provided between the GaN intermediate layer and the high Al composition layer.Type: GrantFiled: January 9, 2015Date of Patent: July 12, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Toshiki Hikosaka, Hisashi Yoshida, Hajime Nago, Shinya Nunoue
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Publication number: 20160163803Abstract: According to one embodiment, a nitride semiconductor element includes a foundation layer, a functional layer and a stacked body. The stacked body is provided between the foundation layer and the functional layer. The stacked body includes a first stacked intermediate layer including a first GaN intermediate layer, a first high Al composition layer of Alx1Ga1-x1N (0<x1?1) and a first low Al composition layer. A compressive strain is applied to the first low Al composition layer. Unstrained GaN has a first lattice spacing. The Alx1Ga1-x1N (0<x1?1) when unstrained has a second lattice spacing. The first high Al composition layer has a third lattice spacing. An Al composition ratio of the first low Al composition layer is not more than a ratio of a difference between the first and third lattice spacings to a difference between the first and second lattice spacings.Type: ApplicationFiled: February 16, 2016Publication date: June 9, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Toshiki HIKOSAKA, Yoshiyuki HARADA, Hisashi YOSHIDA, Naoharu SUGIYAMA, Shinya NUNOUE
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Patent number: 9349590Abstract: According to one embodiment, a method for manufacturing a nitride semiconductor layer is disclosed. The method can include forming a first lower layer on a major surface of a substrate and forming a first upper layer on the first lower layer. The first lower layer has a first lattice spacing along a first axis parallel to the major surface. The first upper layer has a second lattice spacing along the first axis larger than the first lattice spacing. At least a part of the first upper layer has compressive strain. A ratio of a difference between the first and second lattice spacing to the first lattice spacing is not less than 0.005 and not more than 0.019. A growth rate of the first upper layer in a direction parallel to the major surface is larger than that in a direction perpendicular to the major surface.Type: GrantFiled: September 5, 2012Date of Patent: May 24, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Toshiki Hikosaka, Yoshiyuki Harada, Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue
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Semiconductor light emitting device and method for manufacturing semiconductor light emitting device
Patent number: 9331234Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting layer. The p-type semiconductor layer includes a first p-side layer, a second p-side layer, and a third p-side layer. A concentration profile of Mg of a p-side region includes a first portion, a second portion, a third portion, a fourth portion, a fifth portion, a sixth portion and a seventh portion. The p-side region includes the light emitting layer, the second p-side layer, and the third p-side layer. A Mg concentration of the sixth portion is not less than 1×1020 cm?3 and not more than 3×1020 cm?3. The Al concentration is 1/100 of the maximum value at a second position. A Mg concentration at the second position is not less than 2×1018 cm?3.Type: GrantFiled: July 13, 2015Date of Patent: May 3, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hajime Nago, Yoshiyuki Harada, Shigeya Kimura, Hisashi Yoshida, Shinya Nunoue -
Patent number: 9305773Abstract: According to one embodiment, a semiconductor device includes a functional layer of a nitride semiconductor. The functional layer is provided on a nitride semiconductor layer including a first stacked multilayer structure provided on a substrate. The first stacked multilayer structure includes a first lower layer, a first intermediate layer, and a first upper layer. The first lower layer contains Si with a first concentration and has a first thickness. The first intermediate layer is provided on the first lower layer to be in contact with the first lower layer, contains Si with a second concentration lower than the first concentration, and has a second thickness thicker than the first thickness. The first upper layer is provided on the first intermediate layer to be in contact with the first intermediate layer, contains Si with a third concentration lower than the second concentration, and has a third thickness.Type: GrantFiled: June 19, 2015Date of Patent: April 5, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hung Hung, Naoharu Sugiyama, Hisashi Yoshida, Toshiki Hikosaka, Yoshiyuki Harada, Shinya Nunoue
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Patent number: 9287369Abstract: According to one embodiment, a nitride semiconductor element includes a foundation layer, a functional layer and a stacked body. The stacked body is provided between the foundation layer and the functional layer. The stacked body includes a first stacked intermediate layer including a first GaN intermediate layer, a first high Al composition layer of Alx1Ga1-x1N (0<x1?1) and a first low Al composition layer. A compressive strain is applied to the first low Al composition layer. Unstrained GaN has a first lattice spacing. The Alx1Ga1-x1N (0<x1?1) when unstrained has a second lattice spacing. The first high Al composition layer has a third lattice spacing. An Al composition ratio of the first low Al composition layer is not more than a ratio of a difference between the first and third lattice spacings to a difference between the first and second lattice spacings.Type: GrantFiled: January 14, 2014Date of Patent: March 15, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Toshiki Hikosaka, Yoshiyuki Harada, Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue
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Publication number: 20160056329Abstract: According to one embodiment, a semiconductor light emitting element includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type separated from the first semiconductor layer in a first direction, a light emitting layer provided between the first and second semiconductor layers, and a first intermediate unit provided between the first semiconductor layer and the light emitting layer. The light emitting layer includes a well layer including a nitride semiconductor including In. The first intermediate unit includes stacked bodies. The stacked bodies are arranged in the first direction. Each of the stacked bodies includes a first layer of Inx1Ga1-x1N, a second layer of Aly1Ga1-y1N provided between the first layer and the light emitting layer to contact the first layer, and a third layer of Aly2Ga1-y2N provided between the second layer and the light emitting layer to contact the second layer.Type: ApplicationFiled: May 18, 2015Publication date: February 25, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Hisashi YOSHIDA, Toshiki Hikosaka, Shigeya Kimura, Hajime Nago, Shinya Nunoue
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Publication number: 20160043183Abstract: According to one embodiment, a semiconductor wafer includes a substrate, an AlN buffer layer, a foundation layer, a first high Ga composition layer, a high Al composition layer, a low Al composition layer, an intermediate unit and a second high Ga composition layer. The first layer is provided on the foundation layer. The high Al composition layer is provided on the first layer. The low Al composition layer is provided on the high Al composition layer. The intermediate unit is provided on the low Al composition layer. The second layer is provided on the intermediate unit. The first layer has a first tensile strain and the second layer has a second tensile strain larger than the first tensile strain. Alternatively, the first layer has a first compressive strain and the second layer has a second compressive strain smaller than the first compressive strain.Type: ApplicationFiled: October 23, 2015Publication date: February 11, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Yoshiyuki HARADA, Toshiki HIKOSAKA, Hisashi YOSHIDA, Hung HUNG, Naoharu SUGIYAMA, Shinya NUNOUE
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Patent number: 9202873Abstract: According to one embodiment, a semiconductor wafer includes a substrate, an AlN buffer layer, a foundation layer, a first high Ga composition layer, a high Al composition layer, a low Al composition layer, an intermediate unit and a second high Ga composition layer. The first layer is provided on the foundation layer. The high Al composition layer is provided on the first layer. The low Al composition layer is provided on the high Al composition layer. The intermediate unit is provided on the low Al composition layer. The second layer is provided on the intermediate unit. The first layer has a first tensile strain and the second layer has a second tensile strain larger than the first tensile strain. Alternatively, the first layer has a first compressive strain and the second layer has a second compressive strain smaller than the first compressive strain.Type: GrantFiled: April 23, 2013Date of Patent: December 1, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiyuki Harada, Toshiki Hikosaka, Hisashi Yoshida, Hung Hung, Naoharu Sugiyama, Shinya Nunoue
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SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE
Publication number: 20150318435Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting layer. The p-type semiconductor layer includes a first p-side layer, a second p-side layer, and a third p-side layer. A concentration profile of Mg of a p-side region includes a first portion, a second portion, a third portion, a fourth portion, a fifth portion, a sixth portion and a seventh portion. The p-side region includes the light emitting layer, the second p-side layer, and the third p-side layer. A Mg concentration of the sixth portion is not less than 1×1020 cm?3 and not more than 3×1020 cm?3. The Al concentration is 1/100 of the maximum value at a second position. A Mg concentration at the second position is not less than 2×1018 cm?3.Type: ApplicationFiled: July 13, 2015Publication date: November 5, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hajime NAGO, Yoshiyuki HARADA, Shigeya KIMURA, Hisashi YOSHIDA, Shinya NUNOUE -
Publication number: 20150287589Abstract: According to one embodiment, a semiconductor device includes a functional layer of a nitride semiconductor. The functional layer is provided on a nitride semiconductor layer including a first stacked multilayer structure provided on a substrate. The first stacked multilayer structure includes a first lower layer, a first intermediate layer, and a first upper layer. The first lower layer contains Si with a first concentration and has a first thickness. The first intermediate layer is provided on the first lower layer to be in contact with the first lower layer, contains Si with a second concentration lower than the first concentration, and has a second thickness thicker than the first thickness. The first upper layer is provided on the first intermediate layer to be in contact with the first intermediate layer, contains Si with a third concentration lower than the second concentration, and has a third thickness.Type: ApplicationFiled: June 19, 2015Publication date: October 8, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Hung HUNG, Naoharu SUGIYAMA, Hisashi YOSHIDA, Toshiki HIKOSAKA, Yoshiyuki HARADA, Shinya NUNOUE
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Patent number: 9130098Abstract: According to one embodiment, a semiconductor light emitting device includes a light emitting layer, a light transmitting layer and a first semiconductor layer. The light transmitting layer is transmittable with respect to light emitted from the light emitting layer. The first semiconductor layer contacts the light transmitting layer between the light emitting layer and the light transmitting layer. The light transmitting layer has a thermal expansion coefficient larger than a thermal expansion coefficient of the light transmitting layer, has a lattice constant smaller than a lattice constant of the active layer, and has a tensile stress in an in-plane direction.Type: GrantFiled: August 18, 2011Date of Patent: September 8, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Naoharu Sugiyama, Tomonari Shioda, Hisashi Yoshida, Shinya Nunoue
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Patent number: 9130069Abstract: According to one embodiment, a method is disclosed for manufacturing a nitride semiconductor layer. The method can include forming a first nitride semiconductor layer on a substrate in a reactor supplied with a first carrier gas and a first source gas. The first nitride semiconductor layer includes indium. The first carrier gas includes hydrogen supplied into the reactor at a first flow rate and includes nitrogen supplied into the reactor at a second flow rate. The first source gas includes indium and nitrogen and supplied into the reactor at a third flow rate. The first flow rate is not less than 0.07% and not more than 0.15% of a sum of the first flow rate, the second flow rate, and the third flow rate.Type: GrantFiled: March 13, 2013Date of Patent: September 8, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hajime Nago, Yoshiyuki Harada, Hisashi Yoshida, Shigeya Kimura, Shinya Nunoue
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Patent number: 9123831Abstract: According to one embodiment, a semiconductor device includes a functional layer of a nitride semiconductor. The functional layer is provided on a nitride semiconductor layer including a first stacked multilayer structure provided on a substrate. The first stacked multilayer structure includes a first lower layer, a first intermediate layer, and a first upper layer. The first lower layer contains Si with a first concentration and has a first thickness. The first intermediate layer is provided on the first lower layer to be in contact with the first lower layer, contains Si with a second concentration lower than the first concentration, and has a second thickness thicker than the first thickness. The first upper layer is provided on the first intermediate layer to be in contact with the first intermediate layer, contains Si with a third concentration lower than the second concentration, and has a third thickness.Type: GrantFiled: February 28, 2013Date of Patent: September 1, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hung Hung, Naoharu Sugiyama, Hisashi Yoshida, Toshiki Hikosaka, Yoshiyuki Harada, Shinya Nunoue
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Semiconductor light emitting device and method for manufacturing semiconductor light emitting device
Patent number: 9112111Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting layer. The p-type semiconductor layer includes a first p-side layer, a second p-side layer, and a third p-side layer. A concentration profile of Mg of a p-side region includes a first portion, a second portion, a third portion, a fourth portion, a fifth portion, a sixth portion and a seventh portion. The p-side region includes the light emitting layer, the second p-side layer, and the third p-side layer. A Mg concentration of the sixth portion is not less than 1×1020 cm?3 and not more than 3×1020 cm?3. The Al concentration is 1/100 of the maximum value at a second position. A Mg concentration at the second position is not less than 2×1018 cm?3.Type: GrantFiled: December 2, 2013Date of Patent: August 18, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hajime Nago, Yoshiyuki Harada, Shigeya Kimura, Hisashi Yoshida, Shinya Nunoue -
Publication number: 20150221728Abstract: According to one embodiment, a nitride semiconductor device includes a stacked body and a functional layer. The stacked body includes an AlGaN layer of AlxGa1-xN (0<x?1), a first Si-containing layer, a first GaN layer, a second Si-containing layer, and a second GaN layer. The first Si-containing layer contacts an upper surface of the AlGaN layer. The first Si-containing layer contains Si at a concentration not less than 7×1019/cm3 and not more than 4×1020/cm3. The first GaN layer is provided on the first Si-containing layer. The first GaN layer includes a protrusion having an oblique surface tilted with respect to the upper surface. The second Si-containing layer is provided on the first GaN layer. The second Si-containing layer contains Si. The second GaN layer is provided on the second Si-containing layer. The functional layer is provided on the stacked body. The functional layer includes a nitride semiconductor.Type: ApplicationFiled: April 16, 2015Publication date: August 6, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Toshiki HIKOSAKA, Yoshiyuki HARADA, Hisashi YOSHIDA, Naoharu SUGIYAMA, Shinya NUNOUE
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Publication number: 20150200255Abstract: According to one embodiment, a nitride semiconductor element includes a functional layer and a stacked body. The stacked body includes a GaN intermediate layer, a low Al composition layer, a high Al composition layer, and a first Si-containing layer. The low Al composition layer includes a nitride semiconductor having a first Al composition ratio. The low Al composition layer is provided between the GaN intermediate layer and the functional layer. The high Al composition layer includes a nitride semiconductor having a second Al composition ratio. The high Al composition layer is provided between the GaN intermediate layer and the low Al composition layer. The second Al composition ratio is higher than the first Al composition ratio. The first Si-containing layer is provided between the GaN intermediate layer and the high Al composition layer.Type: ApplicationFiled: January 9, 2015Publication date: July 16, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Toshiki Hikosaka, Hisashi Yoshida, Hajime Nago, Shinya Nunoue
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Patent number: 9065004Abstract: In general, according to one embodiment, a semiconductor light emitting element includes: a first semiconductor layer; a second semiconductor layer; a light emitting layer. The light emitting layer includes a well layer with a thickness of t1 (nanometers). The well layer includes InxGa1-xN having an In composition ratio x higher than 0 and lower than 1. The first semiconductor layer has a tensile strain of not less than 0.02 percent and not more than 0.25 percent in a plane perpendicular to a stacking direction. A peak wavelength ?p (nanometers) of light satisfies a relationship of ?p=a1+a2×(x+(t1?3.0)×a3). The a1 is not less than 359 and not more than 363. The a2 is not less than 534 and not more than 550. The a3 is not less than 0.0205 and not more than 0.0235.Type: GrantFiled: July 3, 2014Date of Patent: June 23, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Naoharu Sugiyama, Shigeya Kimura, Hisashi Yoshida, Toshiki Hikosaka, Jumpei Tajima, Hajime Nago, Shinya Nunoue
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Patent number: 9065003Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer and configured to emit a light having a peak wavelength of 440 nanometers or more. Tensile strain is applied to the first semiconductor layer. An edge dislocation density of the first semiconductor layer is 5×109/cm2 or less. A lattice mismatch factor between the first semiconductor layer and the light emitting layer is 0.11 percent or less.Type: GrantFiled: February 27, 2012Date of Patent: June 23, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hisashi Yoshida, Koichi Tachibana, Tomonari Shioda, Toshiki Hikosaka, Jongil Hwang, Hung Hung, Naoharu Sugiyama, Shinya Nunoue