Patents by Inventor Hisato Yabuta

Hisato Yabuta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120040196
    Abstract: Provided are a thermal expansion suppressing member having negative thermal expansion properties and a metal-based anti-thermally-expansive member having small thermal expansion. More specifically, provided are a thermal expansion suppressing member, including at least an oxide represented by the following general formula (1), and an anti-thermally-expansive member, including a metal having a positive linear expansion coefficient at 20° C., and a solid body including at least an oxide represented by the following general formula (1), the metal and solid being joined to each other: (Bi1-xMx)NiO3 (1) where M represents at least one metal selected from the group consisting of La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Y, and In; and x represents a numerical value of 0.02?x?0.15.
    Type: Application
    Filed: August 8, 2011
    Publication date: February 16, 2012
    Applicants: KYOTO UNIVERSITY, CANON KABUSHIKI KAISHA
    Inventors: Makoto Kubota, Kaoru Miura, Hisato Yabuta, Yoshihiko Matsumura, Yuichi Shimakawa, Masaki Azuma
  • Publication number: 20120032173
    Abstract: Provided is a top gate thin film transistor, including on a substrate: a source electrode layer; a drain electrode layer; an oxide semiconductor layer; a gate insulating layer; a gate electrode layer including an amorphous oxide semiconductor containing at least one kind of element selected from among In, Ga, Zn, and Sn; and a protective layer containing hydrogen, in which: the gate insulating layer is formed on a channel region of the oxide semiconductor layer; the gate electrode layer is formed on the gate insulating layer; and the protective layer is formed on the gate electrode layer.
    Type: Application
    Filed: July 21, 2011
    Publication date: February 9, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Ayumu Sato, Hideya Kumomi, Hisato Yabuta, Ryo Hayashi, Yasuyoshi Takai
  • Patent number: 8110436
    Abstract: A method for manufacturing a field-effect transistor is provided. The field-effect transistor includes on a substrate a source electrode, a drain electrode, an oxide semiconductor layer, an insulating layer and a gate electrode. The method includes, after forming the insulating layer on the oxide semiconductor layer, an annealing step of increasing the electrical conductivity of the oxide semiconductor layers by annealing in an atmosphere containing moisture. The steam pressure at the annealing step is higher than the saturated vapor pressure in the atmosphere at the annealing temperature.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: February 7, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ryo Hayashi, Hisato Yabuta, Yoshinori Tateishi, Nobuyuki Kaji
  • Publication number: 20110309356
    Abstract: A method for forming a SnO-containing semiconductor film includes a first step of forming a SnO-containing film; a second step of forming an insulator film composed of an oxide or a nitride on the SnO-containing film to provide a laminated film including the SnO-containing film and the insulator film; and a third step of subjecting the laminated film to a heat treatment.
    Type: Application
    Filed: March 1, 2010
    Publication date: December 22, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hisato Yabuta, Nobuyuki Kaji, Ryo Hayashi
  • Patent number: 8044402
    Abstract: An amorphous insulator film is provided which is composed of silicon (Si) oxide, in which the amorphous insulator film includes Ar and an amount of Ar included therein is equal to or larger than 3 at. % in terms of atomic ratio with respect to Si.
    Type: Grant
    Filed: February 2, 2008
    Date of Patent: October 25, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hisato Yabuta, Nobuyuki Kaji, Ryo Hayashi
  • Publication number: 20110221302
    Abstract: Provided is a lead-free dielectric ceramics having a low leakage current value, and a bismuth iron oxide powder as a raw material thereof. The bismuth iron oxide powder includes at least: (A) grains including a bismuth iron oxide having a perovskite-type crystal structure; (B) grains including a bismuth iron oxide having a crystal structure classified to a space group Pbam; and (C) grains including a bismuth iron oxide or a bismuth oxide having a crystal structure that is classified to a space group I23. The dielectric ceramics are made of bismuth iron oxide in which the bismuth iron oxide crystals having the crystal structure classified to the space group Pbam are distributed at a grain boundary of crystal grains of the bismuth iron oxide crystals having the perovskite-type crystal structure.
    Type: Application
    Filed: March 10, 2011
    Publication date: September 15, 2011
    Applicants: CANON KABUSHIKI KAISHA, FUJI CHEMICAL CO., LTD.
    Inventors: Hisato Yabuta, Makoto Kubota, Mikio Shimada, Kenji Takashima, Fumio Uchida, Kenji Maeda, Chiemi Shimizu
  • Publication number: 20110168905
    Abstract: An X-ray detector includes an X-ray photoelectric conversion layer configured to produce electric charges in proportion to X-ray irradiation incident on the layer, a collecting electrode configured to collect the electric charges produced by the X-ray photoelectric conversion layer, a common electrode disposed on a surface of the X-ray photoelectric conversion layer opposite to the collecting electrode, a storage capacitor configured to store the electric charges collected by the collecting electrode, and a readout unit configured to read out the electric charges stored in the storage capacitor. A voltage is to be applied between the collecting electrode and the common electrode. The X-ray photoelectric conversion layer is formed of a polycrystalline oxide.
    Type: Application
    Filed: January 4, 2011
    Publication date: July 14, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hisato Yabuta, Nobuyuki Kaji, Ryo Hayashi, Masatoshi Watanabe, Taihei Mukaide, Kazunori Fukuda
  • Publication number: 20110062441
    Abstract: Provided is a semiconductor device including a semiconductor element including at least a semiconductor as a component characterized by including: a mechanism for irradiating the semiconductor with light having a wavelength longer than an absorption edge wavelength of the semiconductor; and a dimming mechanism, provided in a part of an optical path through which the light passes, for adjusting at least one factor selected from an intensity, irradiation time and the wavelength of the light, wherein a threshold voltage of the semiconductor element is varied by the light adjusted by the dimming mechanism.
    Type: Application
    Filed: May 11, 2009
    Publication date: March 17, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hisato Yabuta, Masato Ofuji, Yasuyoshi Takai, Takehiko Kawasaki, Norio Kaneko, Ryo Hayashi
  • Publication number: 20110042670
    Abstract: Provided are a coplanar structure thin film transistor that allows a threshold voltage to change only a little under electric stress, and a method of manufacturing the same. The thin film transistor includes on a substrate at least: a gate electrode; a gate insulating layer; an oxide semiconductor layer including a source electrode, a drain electrode, and a channel region; a channel protection layer; and an interlayer insulating layer. The channel protection layer includes one or more layers, the layer in contact with the oxide semiconductor layer among the one or more layers being made of an insulating material containing oxygen, ends of the channel protection layer are thinner than a central part of the channel protection layer, the interlayer insulating layer contains hydrogen, and regions of the oxide semiconductor layer that are in direct contact with the interlayer insulating layer form the source electrode and the drain electrode.
    Type: Application
    Filed: April 28, 2009
    Publication date: February 24, 2011
    Applicant: Canon Kabushiki Kaisha
    Inventors: Ayumu Sato, Ryo Hayashi, Hisato Yabuta, Masafumi Sano
  • Patent number: 7883934
    Abstract: A method for fabricating a device using an oxide semiconductor, including a process of forming the oxide semiconductor on a substrate and a process of changing the conductivity of the oxide semiconductor by irradiating a predetermined region thereof with an energy ray.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: February 8, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuyuki Kaji, Hisato Yabuta
  • Publication number: 20100283049
    Abstract: Provided is an oxide semiconductor device including an oxide semiconductor layer and an insulating layer coming into contact with the oxide semiconductor layer in which the insulating layer includes: a first insulating layer coming into contact with an oxide semiconductor, having a thickness of 50 nm or more, and including an oxide containing Si and O; a second insulating layer coming into contact with the first insulating layer, having a thickness of 50 nm or more, and including a nitride containing Si and N; and a third insulating layer coming into contact with the second insulating layer, the first insulating layer and the second insulating layer having hydrogen contents of 4×1021 atoms/cm3 or less, and the third insulating layer having a hydrogen content of more than 4×1021 atoms/cm3.
    Type: Application
    Filed: November 27, 2008
    Publication date: November 11, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Ayumu Sato, Ryo Hayashi, Hisato Yabuta, Tomohiro Watanabe
  • Patent number: 7829444
    Abstract: Provided is a novel method for manufacturing a field effect transistor. Prior to forming an amorphous oxide layer on a substrate, ultraviolet rays are irradiated onto the substrate surface in an ozone atmosphere, plasma is irradiated onto the substrate surface, or the substrate surface is cleaned by a chemical solution containing hydrogen peroxide.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: November 9, 2010
    Assignees: Canon Kabushiki Kaisha, Tokyo Institute of Technology
    Inventors: Hisato Yabuta, Masafumi Sano, Tatsuya Iwasaki, Hideo Hosono, Toshio Kamiya, Kenji Nomura
  • Publication number: 20100267198
    Abstract: Provided is a novel method for manufacturing a field effect transistor. Prior to forming an amorphous oxide layer on a substrate, ultraviolet rays are irradiated onto the substrate surface in an ozone atmosphere, plasma is irradiated onto the substrate surface, or the substrate surface is cleaned by a chemical solution containing hydrogen peroxide.
    Type: Application
    Filed: June 28, 2010
    Publication date: October 21, 2010
    Applicants: CANON KABUSHIKI KAISHA, TOKYO INSTITUTE OF TECHNOLOGY
    Inventors: HISATO YABUTA, MASAFUMI SANO, TATSUYA IWASAKI, HIDEO HOSONO, Toshio Kamiya, KENJI NOMURA
  • Publication number: 20100203673
    Abstract: A method for manufacturing a field-effect transistor is provided. The field-effect transistor includes on a substrate a source electrode, a drain electrode, an oxide semiconductor layer, an insulating layer and a gate electrode. The method includes, after forming the insulating layer on the oxide semiconductor layer, an annealing step of increasing the electrical conductivity of the oxide semiconductor layers by annealing in an atmosphere containing moisture. The steam pressure at the annealing step is higher than the saturated vapor pressure in the atmosphere at the annealing temperature.
    Type: Application
    Filed: September 25, 2008
    Publication date: August 12, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Ryo Hayashi, Hisato Yabuta, Yoshinori Tateishi, Nobuyuki Kaji
  • Publication number: 20100144089
    Abstract: A method for fabricating a device using an oxide semiconductor, including a process of forming the oxide semiconductor on a substrate and a process of changing the conductivity of the oxide semiconductor by irradiating a predetermined region thereof with an energy ray.
    Type: Application
    Filed: February 19, 2010
    Publication date: June 10, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: NOBUYUKI KAJI, HISATO YABUTA
  • Patent number: 7691715
    Abstract: A method for fabricating a device using an oxide semiconductor, including a process of forming the oxide semiconductor on a substrate and a process of changing the conductivity of the oxide semiconductor by irradiating a predetermined region thereof with an energy ray.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: April 6, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuyuki Kaji, Hisato Yabuta
  • Publication number: 20100065837
    Abstract: A thin film transistor is manufactured by forming a gate electrode on a substrate, forming a first insulating film on the gate electrode, forming an oxide semiconductor layer on the first insulating film with an amorphous oxide, patterning the first insulating film, patterning the oxide semiconductor layer, forming a second insulating film on the oxide semiconductor layer in an oxidative-gas-containing atmosphere, patterning the second insulating film to expose a pair of contact regions, forming an electrode layer on the pair of contact regions, and patterning the electrode layer to for a source electrode and a drain electrode.
    Type: Application
    Filed: November 29, 2007
    Publication date: March 18, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hideyuki Omura, Ryo Hayashi, Nobuyuki Kaji, Hisato Yabuta
  • Publication number: 20100051947
    Abstract: An amorphous insulator film is provided which is composed of silicon (Si) oxide, in which the amorphous insulator film includes Ar and an amount of Ar included therein is equal to or larger than 3 at. % in terms of atomic ratio with respect to Si.
    Type: Application
    Filed: February 2, 2008
    Publication date: March 4, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hisato Yabuta, Nobuyuki Kaji, Ryo Hayashi
  • Publication number: 20100051936
    Abstract: Provided is a bottom gate type thin film transistor including on a substrate (1) a gate electrode (2), a first insulating film (3) as a gate insulating film, an oxide semiconductor layer (4) as a channel layer, a second insulating film (5) as a protective layer, a source electrode (6), and a drain electrode (7), in which the oxide semiconductor layer (4) includes an oxide including at least one selected from the group consisting of In, Zn, and Sn, and the second insulating film (5) includes an amorphous oxide insulator formed so as to be in contact with the oxide semiconductor layer (4) and contains therein 3.8×1019 molecules/cm3 or more of a desorbed gas observed as oxygen by temperature programmed desorption mass spectrometry.
    Type: Application
    Filed: November 20, 2007
    Publication date: March 4, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Ryo Hayashi, Nobuyuki Kaji, Hisato Yabuta
  • Publication number: 20100051937
    Abstract: There is provided a thin-film transistor including at least a substrate, a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode, a drain electrode and a protective layer, wherein the oxide semiconductor layer is an amorphous oxide containing at least one of the elements In, Ga and Zn, the gate electrode-side carrier density of the oxide semiconductor layer is higher than the protective layer-side carrier density thereof, and the film thickness of the oxide semiconductor layer is 30 nm±15 nm.
    Type: Application
    Filed: February 8, 2008
    Publication date: March 4, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Nobuyuki Kaji, Ryo Hayashi, Hisato Yabuta, Katsumi Abe