Patents by Inventor Hisayoshi Kajiwara

Hisayoshi Kajiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10191588
    Abstract: A capacitance detection device of a capacitance system includes: a capacitance sensor electrode for detecting a capacitance; a power source for supplying charges to be charged in the capacitance sensor electrode; an electric charge storage capacitor in which an amount of charges to be charged therein changes according to the electric charges charged in the capacitance sensor electrode; and a switch for changing a reference potential of the electric charge storage capacitor. The reference potential of the electric charge storage capacitor is changed in a period of measuring the capacitance.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: January 29, 2019
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Norio Mamba, Koji Nagata, Koji Hayakawa, Kouichi Anno, Toshiyuki Kumagai, Tsutomu Furuhashi, Hisayoshi Kajiwara
  • Publication number: 20160313862
    Abstract: A capacitance detection device of a capacitance system includes: a capacitance sensor electrode for detecting capacitance; a power source for supplying charges to be charged in the capacitance sensor electrode; an electric charge storage capacitor in which an amount of charges to be charged therein changes according to the electric charges charged in the capacitance sensor electrode; and a switch for changing a reference potential of the electric charge storage capacitor. The reference potential of the electric charge storage capacitor is changed in a period of measuring the capacitance.
    Type: Application
    Filed: June 21, 2016
    Publication date: October 27, 2016
    Inventors: Norio MAMBA, Koji Nagata, Koji Hayakawa, Kouichi Anno, Toshiyuki Kumagai, Tsutomu Furuhashi, Hisayoshi Kajiwara
  • Patent number: 9395850
    Abstract: A capacitance detection device of a capacitance system includes: a capacitance sensor electrode for detecting a capacitance; a power source for supplying charges to be charged in the capacitance sensor electrode; an electric charge storage capacitor in which an amount of charges to be charged therein changes according to the electric charges charged in the capacitance sensor electrode; and a switch for changing a reference potential of the electric charge storage capacitor. The reference potential of the electric charge storage capacitor is changed in a period of measuring the capacitance.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: July 19, 2016
    Assignees: JAPAN DISPLAY INC., PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
    Inventors: Norio Mamba, Koji Nagata, Koji Hayakawa, Kouichi Anno, Toshiyuki Kumagai, Tsutomu Furuhashi, Hisayoshi Kajiwara
  • Patent number: 9354741
    Abstract: The touch panel controller activates a touch panel having a detection plane superposed on a display plane of a display device, and performs a touch detection. The touch panel controller uses a cycle of 1/n (n is a positive integer) of a display frame cycle on the display plane as the detection frame cycle of the detection plane. The touch panel controller decides an order of driving the detection-scan electrodes in each detection frame cycle according to predetermined phase-delay and phase-advance positions with respect to a display-scan electrode drive position of the display device so as to correspond to an order of the detection-scan electrode array of the touch panel. The touch panel controller makes possible to avoid the coincidence of display-scan and touch-detection positions without thinning touch detections even with the detection frame cycle of a touch sensor shorter than the display frame cycle of a liquid crystal panel.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: May 31, 2016
    Assignee: Synaptics Display Devices GK
    Inventors: Yusuke Uchida, Tatsuya Ishii, Tsuyoshi Kuroiwa, Akihito Akai, Hisayoshi Kajiwara, Kazuo Okado
  • Publication number: 20140210750
    Abstract: The touch panel controller activates a touch panel having a detection plane superposed on a display plane of a display device, and performs a touch detection. The touch panel controller uses a cycle of 1/n (n is a positive integer) of a display frame cycle on the display plane as the detection frame cycle of the detection plane. The touch panel controller decides an order of driving the detection-scan electrodes in each detection frame cycle according to predetermined phase-delay and phase-advance positions with respect to a display-scan electrode drive position of the display device so as to correspond to an order of the detection-scan electrode array of the touch panel. The touch panel controller makes possible to avoid the coincidence of display-scan and touch-detection positions without thinning touch detections even with the detection frame cycle of a touch sensor shorter than the display frame cycle of a liquid crystal panel.
    Type: Application
    Filed: January 29, 2014
    Publication date: July 31, 2014
    Applicant: Renesas SP Drivers Inc.
    Inventors: Yusuke Uchida, Tatsuya Ishii, Tsuyoshi Kuroiwa, Akihito Akai, Hisayoshi Kajiwara, Kazuo Okado
  • Patent number: 8102357
    Abstract: An inverter includes an input inverter having a high-resistance load and a first transistor and an output buffer including second and third transistors coupled in series. A power supply voltage is provided to satisfy an inequality VDD1>VDD2+Vth where VDD1 is the power supply voltage of the input inverter, VDD2 is the power supply voltage of the output buffer, and Vth is the threshold voltage of the transistors. Use of the high-resistance load allows an output waveform to rise and fall quickly, as well as reduces current consumption.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: January 24, 2012
    Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Hisayoshi Kajiwara, Norio Mamba, Toshio Miyazawa, Masahiro Maki
  • Publication number: 20100085322
    Abstract: A capacitance detection device of a capacitance system includes: a capacitance sensor electrode for detecting a capacitance; a power source for supplying charges to be charged in the capacitance sensor electrode; an electric charge storage capacitor in which an amount of charges to be charged therein changes according to the electric charges charged in the capacitance sensor electrode; and a switch for changing a reference potential of the electric charge storage capacitor. The reference potential of the electric charge storage capacitor is changed in a period of measuring the capacitance.
    Type: Application
    Filed: October 6, 2009
    Publication date: April 8, 2010
    Inventors: Norio MAMBA, Koji Nagata, Koji Hayakawa, Kouichi Anno, Toshiyuki Kumagai, Tsutomu Furuhashi, Hisayoshi Kajiwara
  • Patent number: 7548109
    Abstract: A booster circuit of a two-step booster structure is manufactured by NMOS single channel processes and has two basic booster circuits to raise a gate voltage of a charge transfer transistor. The gate voltage of the transistor is first raised at one basic booster circuit, and this raised voltage is further raised at the other basic booster circuit.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: June 16, 2009
    Assignee: Hitachi Displays, Ltd.
    Inventors: Hisayoshi Kajiwara, Norio Mamba, Toshio Miyazawa
  • Publication number: 20080278650
    Abstract: An inverter includes an input inverter having a high-resistance load and a first transistor and an output buffer including second and third transistors coupled in series. A power supply voltage is provided to satisfy an inequality VDD1>VDD2+Vth where VDD1 is the power supply voltage of the input inverter, VDD2 is the power supply voltage of the output buffer, and Vth is the threshold voltage of the transistors. Use of the high-resistance load allows an output waveform to rise and fall quickly, as well as reduces current consumption.
    Type: Application
    Filed: April 10, 2008
    Publication date: November 13, 2008
    Inventors: Hisayoshi KAJIWARA, Norio Mamba, Toshio Miyazawa, Masahiro Maki
  • Patent number: 7424276
    Abstract: In a transmitter of polar-loop architecture having a phase control loop and an amplitude control loop, as loop filters for controlling a loop band of the amplitude control loop, a first filter with lag-lead characteristics (secondary or more filter including a capacitor and a resistor) and a second filter of a perfect integrator type (filter including only a capacitor) are employed, and current-output type circuits are connected to respective front stages of the first and second filters.
    Type: Grant
    Filed: February 18, 2003
    Date of Patent: September 9, 2008
    Assignees: Renesas Technology Corp., TTPCOM Limited
    Inventors: Taizo Yamawaki, Hisayoshi Kajiwara, Ryoichi Takano, Patrick Wurm
  • Publication number: 20080054992
    Abstract: A booster circuit of a two-step booster structure is manufactured by NMOS single channel processes and has two basic booster circuits to raise a gate voltage of a charge transfer transistor. The gate voltage of the transistor is first raised at one basic booster circuit, and this raised voltage is further raised at the other basic booster circuit.
    Type: Application
    Filed: July 30, 2007
    Publication date: March 6, 2008
    Inventors: Hisayoshi Kajiwara, Norio Mamba, Toshio Miyazawa
  • Publication number: 20070142012
    Abstract: A wireless communication receiver that is able to lessen the effect of noise that accompanies gain change by programmable gain amplifiers. The receiver includes an AGC controller which controls the timing at which the programmable gain amplifiers make gain change, using a terminal counter and a sequencer. The receiver prevents gain change noise signals during the reception of control signals and other signals that are susceptible to noise. By the timing control feature, the programmable gain amplifiers make gain change while reducing noise impact.
    Type: Application
    Filed: February 6, 2007
    Publication date: June 21, 2007
    Inventors: Yukinori Akamine, Hisayoshi Kajiwara, Satoshi Tanaka, Takashi Yano, Hirotake Ishii, Akio Yamamoto, Kazuaki Hori, Kazuhiko Hikasa
  • Publication number: 20070091053
    Abstract: Output voltages of R-2R ladder resistor type digital-to-analog conversion circuits are once stored in sample and hold capacitors through sample and hold charging amplifiers and the voltages stored in the capacitors are then supplied to a liquid crystal panel through panel drive amplifiers and multiplexers simultaneously. Power supplies to the digital-to-analog conversion circuits and the charging amplifiers are turned on by means of switches only during the period that the voltages are written in the capacitors and turned off during other periods. Two systems of the capacitors and the panel drive amplifiers are provided in order to make the operation of charging the analog voltages to the capacitors and the operation of taking out the analog voltages stored in the capacitors to supply the voltages to the liquid crystal panel in parallel.
    Type: Application
    Filed: October 11, 2006
    Publication date: April 26, 2007
    Inventors: Hisayoshi Kajiwara, Tsutomu Furuhashi, Hiroyuki Nitta, Naoki Takada
  • Patent number: 7194244
    Abstract: A wireless communication receiver that is able to lessen the effect of noise that accompanies gain change by programmable gain amplifiers. The receiver includes an AGC controller which controls the timing at which the programmable gain amplifiers make gain change, using a terminal counter and a sequencer. The receiver prevents gain change noise signals during the reception of control signals and other signals that are susceptible to noise. By the timing control feature, the programmable gain amplifiers make gain change while reducing noise impact.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: March 20, 2007
    Assignee: Renesas Technology Corporation
    Inventors: Yukinori Akamine, Hisayoshi Kajiwara, Satoshi Tanaka, Takashi Yano, Hirotake Ishii, Akio Yamamoto, Kazuaki Hori, Kazuhiko Hikasa
  • Publication number: 20050233714
    Abstract: A variable gain amplifier of low amplitude distortion, and low noise, having a large variable range, is provided. A variable gain differential amplifier that controls a gain by use of bias current is used as each of unit amplifiers (VGAs) making up the variable gain amplifier. A large variable gain range is obtained by series-connecting a plurality of the variable gain differential amplifiers. An attenuator is installed on the input side of the unit amplifier (VGA) at least in the initial stage. By doing so, it becomes possible to prevent amplitude distortion from occurring to the respective VGAs. An attenuator utilizing voltage division by capacitors, generating no noise, is used for lowering noise. Further, the variable gain amplifier is provided with a fixed gain amplifier installed in the final stage as necessary in order to obtain a total gain as desired.
    Type: Application
    Filed: June 10, 2005
    Publication date: October 20, 2005
    Inventors: Hisayoshi Kajiwara, Kenji Toyota, Kazuhiko Hikasa, Taizo Yamawaki
  • Patent number: 6930549
    Abstract: A variable gain amplifier of low amplitude distortion, and low noise, having a large variable range, is provided. A variable gain differential amplifier that controls a gain by use of bias current is used as each of unit amplifiers (VGAs) making up the variable gain amplifier. A large variable gain range is obtained by series-connecting a plurality of the variable gain differential amplifiers. An attenuator is installed on the input side of the unit amplifier (VGA) at least in the initial stage. By doing so, it becomes possible to prevent amplitude distortion from occurring to the respective VGAs. An attenuator utilizing voltage division by capacitors, generating no noise, is used for lowering noise. Further, the variable gain amplifier is provided with a fixed gain amplifier installed in the final stage as necessary in order to obtain a total gain as desired.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: August 16, 2005
    Assignee: Renesas Technology Corporation
    Inventors: Hisayoshi Kajiwara, Kenji Toyota, Kazuhiko Hikasa, Taizo Yamawaki
  • Publication number: 20050176388
    Abstract: In a transmitter of polar-loop architecture having a phase control loop and an amplitude control loop, as loop filters for controlling a loop band of the amplitude control loop, a first filter with lag-lead characteristics (secondary or more filter including a capacitor and a resistor) and a second filter of a perfect integrator type (filter including only a capacitor) are employed, and current-output type circuits are connected to respective front stages of the first and second filters.
    Type: Application
    Filed: February 18, 2003
    Publication date: August 11, 2005
    Inventors: Taizo Yamawaki, Hisayoshi Kajiwara, Ryoichi Takano, Patrick Wurm
  • Publication number: 20040061554
    Abstract: A variable gain amplifier of low amplitude distortion, and low noise, having a large variable range, is provided. A variable gain differential amplifier that controls a gain by use of bias current is used as each of unit amplifiers (VGAs) making up the variable gain amplifier. A large variable gain range is obtained by series-connecting a plurality of the variable gain differential amplifiers. An attenuator is installed on the input side of the unit amplifier (VGA) at least in the initial stage. By doing so, it becomes possible to prevent amplitude distortion from occurring to the respective VGAs. An attenuator utilizing voltage division by capacitors, generating no noise, is used for lowering noise. Further, the variable gain amplifier is provided with a fixed gain amplifier installed in the final stage as necessary in order to obtain a total gain as desired.
    Type: Application
    Filed: May 29, 2003
    Publication date: April 1, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Hisayoshi Kajiwara, Kenji Toyota, Kazuhiko Hikasa, Taizo Yamawaki
  • Publication number: 20030064696
    Abstract: The disclosed invention provides a wireless communication receiver that is able to lessen the effect of noise that accompanies gain change by programmable gain amplifiers. Such noise is produced when direct conversion type programmable gain amplifiers by which gains are adjustable in steps are used for gain control of signals of CDMA or the like in which reception is not intermitted.
    Type: Application
    Filed: September 25, 2002
    Publication date: April 3, 2003
    Inventors: Yukinori Akamine, Hisayoshi Kajiwara, Satoshi Tanaka, Takashi Yano, Hirotake Ishii, Akio Yamamoto, Kazuaki Hori, Kazuhiko Hikasa