Patents by Inventor Hitoshi Ito

Hitoshi Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160324747
    Abstract: The present invention provides a low-toxicity sophorolipid-containing composition. The low-toxicity sophorolipid-containing composition contains at least a coloring component, an acidic sophorolipid, a fatty acid, and a hydroxy fatty acid that are derived from an SL-producing yeast culture. The composition contains the following components in the following proportions, in terms of dry weight, based on the total amount of the acidic sophorolipid, a lactonic sophorolipid, the fatty acid, and the hydroxy fatty acid in the composition taken as 100 mass %: (1) acidic sophorolipid: 94 to 99.99 mass %, (2) lactonic sophorolipid: 0 to 2 mass %, (3) total amount of fatty acid and hydroxy fatty acid: 0.
    Type: Application
    Filed: March 4, 2016
    Publication date: November 10, 2016
    Applicant: Saraya Co., Ltd.
    Inventors: Hitoshi Ito, Michiaki Araki, Yoshihiko Hirata
  • Patent number: 9308229
    Abstract: A method of inhibiting angiogenesis by applying a kind of protein polysaccharide of a (1?6)-?-D-glucan obtained from a residue of extraction of crushed dried fruiting body of Agaricus blazei Murill (himematsutake) with 80% ethanol aqueous solution and hot water at 100 degrees C.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: April 12, 2016
    Assignees: Powerful Healthy Food Corporation, Sun Chlorella Corp.
    Inventors: Hitoshi Ito, Hiroko Itoh, Masaki Fujishima, Yukari Arakawa, Fukuyoshi Nakada
  • Publication number: 20150359829
    Abstract: A method of inhibiting angiogenesis by applying a kind of protein polysaccharide of a (1?6)-?-D-glucan obtained from a residue of extraction of crushed dried fruiting body of Agaricus blazei Murill (himematsutake) with 80% ethanol aqueous solution and hot water at 100 degrees C.
    Type: Application
    Filed: August 24, 2015
    Publication date: December 17, 2015
    Inventors: Hitoshi ITO, Hiroko ITOH, Masaki FUJISHIMA, Yukari ARAKAWA, Fukuyoshi NAKADA
  • Publication number: 20150221400
    Abstract: The shaft sealing structure includes a seal ring that has abutment portions formed by dividing the seal ring along the axial direction and that is provided around a main shaft in a ring-like manner; a support member that is provided in the seal ring along the circumferential direction of the main shaft; and a thermoswitch that is connected to the support member between the abutment portions and that presses the support member toward the center of the main shaft when the temperature rises to a temperature higher than that during normal operation, in which the seal ring is fixed at a position separated from the main shaft during the normal operation and is moved by the support member toward the center of the main shaft when the temperature rises to a temperature higher than that during the normal operation.
    Type: Application
    Filed: September 27, 2013
    Publication date: August 6, 2015
    Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Kentarou Saeki, Hidekazu Uehara, Akihiko Umeda, Masaru Sakai, Hiroshi Kuzumi, Yasuhiro Ikeda, Toshihiko Matsuo, Takanobu Otani, Hiroomi Sakuma, Hitoshi Ito, Yasushi Takayama, Tomoki Hanada, Yuji Harada
  • Publication number: 20150112049
    Abstract: The present invention provides a high-purity acid-form sophorolipid (SL)-containing composition characterized by substantially not containing acetic acid. The high-purity acid-form SL-containing composition can be produced, for example, by the following method: (i) adjusting the pH of a partially purified acid-form SL-containing composition to an acidic range; and (ii-a) subjecting an acidified partially purified acid-form SL-containing composition obtained in step (i) to chromatography to acquire a fraction containing an acid-form SL, or (ii-b) leaving the acidified partially purified acid-form SL-containing composition obtained in step (i) to stand under a low-temperature condition to acquire a resulting gelled object.
    Type: Application
    Filed: March 1, 2013
    Publication date: April 23, 2015
    Applicant: Saraya Co., Ltd.
    Inventors: Yoshihiko Hirata, Mizuyuki Ryu, Hitoshi Ito, Michiaki Araki
  • Publication number: 20130345137
    Abstract: A method of inhibiting angiogenesis by applying a protein polysaccharide of a (1?6)-?-D-glucan with a glucan:protein ratio of 55:43 [w/w], obtained by extracting with a 5 w % aqueous solution of sodium hydroxide a residue of extraction and removal of water-soluble polysaccharides from the Agaricus blazei Murill (himematsutake) fruiting body, and a food/beverage composition for angiogenesis inhibition containing the protein polysaccharide of (1?6)-?-D-glucan.
    Type: Application
    Filed: February 6, 2013
    Publication date: December 26, 2013
    Applicants: SUN CHLORELLA CORP., Powerful Healthy Food Corporation
    Inventors: Hitoshi ITO, Hiroko ITOH, Masaki FUJISHIMA, Yukari ARAKAWA, Fukuyoshi NAKADA
  • Patent number: 8536696
    Abstract: A package substrate including an outermost interlayer resin insulating layer, a pad structure formed on the outermost interlayer resin insulating layer, a conductive connecting pin for establishing an electrical connection with another substrate, the conductive connecting pin being secured to the pad structure via a solder, and via holes formed through the outermost interlayer resin insulating layer and for electrically connecting the pad structure to one or more conductive circuits formed below the outermost interlayer resin insulating layer, the via holes being positioned directly below the pad structure.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: September 17, 2013
    Assignee: Ibiden Co., Ltd.
    Inventors: Naohiro Hirose, Hitoshi Ito, Yoshiyuki Iwata, Masanori Kawade, Hajime Yazu
  • Patent number: 8237211
    Abstract: A non-volatile semiconductor storage device has a memory string including a plurality of electrically rewritable memory cells connected in series. The non-volatile semiconductor storage device also has a protruding layer formed to protrude upward with respect to a substrate. The memory string includes: a plurality of first conductive layers laminated on the substrate; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and an electric charge storage layer formed between the first conductive layers and the first semiconductor layer, and configured to be able to store electric charges. Each of the plurality of first conductive layers includes: a bottom portion extending in parallel to the substrate; and a side portion extending upward with respect to the substrate along the protruding layer at the bottom portion. The protruding layer has a width in a first direction parallel to the substrate that is less than or equal to its length in a lamination direction.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: August 7, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Hiroyasu Tanaka, Masaru Kidoh, Yosuke Komori, Megumi Ishiduki, Akihiro Nitayama, Hideaki Aochi, Hitoshi Ito, Yasuyuki Matsuoka
  • Publication number: 20120032246
    Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a semiconductor substrate, a memory cell transistor formed in a memory cell region, and a field-effect transistor formed in a peripheral circuit region. The memory cell transistor includes: a floating gate electrode; a first inter-electrode insulating film; and a control gate electrode. The field-effect transistor includes: a lower gate electrode; a second inter-electrode insulating film having an opening; and an upper gate electrode electrically connected to the lower gate electrode via the opening. The control gate electrode and the upper gate electrode are formed by a plurality of conductive films that are stacked. The control gate electrode and the upper gate electrode include a barrier film formed in one of interfaces between the stacked conductive films and configured to suppress diffusion of metal atoms. The control gate electrode and the upper gate electrode have a part that is silicided.
    Type: Application
    Filed: August 2, 2011
    Publication date: February 9, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masashi HONDA, Hitoshi Ito, Hideyuki Kinoshita
  • Patent number: 8110917
    Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a motherboard and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: February 7, 2012
    Assignee: IBIDEN Co., Ltd.
    Inventors: Naohiro Hirose, Hitoshi Ito, Yoshiyuki Iwata, Masanori Kawade, Hajime Yazu
  • Patent number: 8105938
    Abstract: There is provided a method of manufacturing a semiconductor substrate. The method includes: (a) forming a wiring pattern on a substrate; (b) covering the wiring pattern with an insulating resin, thereby forming a first insulating layer; (c) forming a second insulating layer on the first insulating layer; (d) forming a plurality of grooves through the second insulating layer; (e) forming at least one via hole through the first and second insulating layers by irradiating at least one of the grooves with a laser beam; (f) forming a seed metal layer on an inner surface of the at least one via hole, inner surfaces of the grooves, and a surface of the second insulating layer; and (g) forming a plating layer in the at least one via hole and the grooves, by an electrolytic plating using the seed metal layer as a power feeding layer.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: January 31, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Hitoshi Ito
  • Patent number: 8035214
    Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a mother board and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.
    Type: Grant
    Filed: November 17, 1999
    Date of Patent: October 11, 2011
    Assignee: IBIDEN Co., Ltd.
    Inventors: Naohiro Hirose, Hitoshi Ito, Yoshiyuki Iwata, Masanori Kawade, Hajime Yazu
  • Patent number: 8013383
    Abstract: A nonvolatile semiconductor storage device has a plurality of memory strings in which a plurality of electrically rewritable memory cells are connected in series. The memory string has a columnar semiconductor layer extending in a direction perpendicular to a substrate; a conductive layer formed so as to sandwich a charge storing layer in cooperation with the columnar semiconductor layer; and a metal layer formed so as to be in contact with the top face of the conductive layer.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: September 6, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kidoh, Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi, Akihiro Nitayama, Hitoshi Ito, Yasuyuki Matsuoka
  • Patent number: 7902659
    Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a mother board and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: March 8, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Naohiro Hirose, Hitoshi Ito, Yoshiyuki Iwata, Masanori Kawade, Hajime Yazu
  • Patent number: 7847393
    Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a mother board and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: December 7, 2010
    Assignee: IBIDEN Co., Ltd.
    Inventors: Naohiro Hirose, Hitoshi Ito, Yoshiyuki Iwata, Masanori Kawade, Hajime Yazu
  • Patent number: 7777601
    Abstract: A movable contacting device in a circuit breaker comprises: a crossbar linked with the opening/closing mechanism and carried so as to pivot cooperatively with the opening/closing mechanism; a movable contact arm engaged, so as to cooperational with the crossbar, with a shaft fitted into a mutually opposing recesses in the crossbar; and a movable contact arm support fixed to the case accomodating the opening/closing mechanism and having mutually opposing through-holes through which the shaft is passed; and the movable contact being configured so that the movable contact slides between surfaces of movable contact arm support having the mutually opposing through-holes; and the construction of a single-pole portion of the movable contact arm is constituted by arranging in parallel two movable contact arm members each having a movable contact at one end, and in a shaft-supporting portion at the other end, an elastic member is sandwiched between the two movable contact arm members.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: August 17, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroyuki Kakisako, Hitoshi Ito, Kozo Maeta, Masanori Kawamura, Shigeki Koumoto
  • Publication number: 20100096682
    Abstract: A non-volatile semiconductor storage device has a memory string including a plurality of electrically rewritable memory cells connected in series. The non-volatile semiconductor storage device also has a protruding layer formed to protrude upward with respect to a substrate. The memory string includes: a plurality of first conductive layers laminated on the substrate; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and an electric charge storage layer formed between the first conductive layers and the first semiconductor layer, and configured to be able to store electric charges. Each of the plurality of first conductive layers includes: a bottom portion extending in parallel to the substrate; and a side portion extending upward with respect to the substrate along the protruding layer at the bottom portion. The protruding layer has a width in a first direction parallel to the substrate that is less than or equal to its length in a lamination direction.
    Type: Application
    Filed: September 9, 2009
    Publication date: April 22, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Hiroyasu Tanaka, Masaru Kidoh, Yosuke Komori, Megumi Ishiduki, Akihiro Nitayama, Hideaki Aochi, Hitoshi Ito, Yasuyuki Matsuoka
  • Publication number: 20100032200
    Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a motherboard and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.
    Type: Application
    Filed: October 19, 2009
    Publication date: February 11, 2010
    Applicant: IBIDEN CO., LTD.
    Inventors: Naohiro HIROSE, Hitoshi Ito, Yoshiyuki Iwata, Masanori Kawade, Hajime Yazu
  • Publication number: 20090314537
    Abstract: A package substrate including an outermost interlayer resin insulating layer, a pad structure formed on the outermost interlayer resin insulating layer, a conductive connecting pin for establishing an electrical connection with another substrate, the conductive connecting pin being secured to the pad structure via a solder, and via holes formed through the outermost interlayer resin insulating layer and for electrically connecting the pad structure to one or more conductive circuits formed below the outermost interlayer resin insulating layer, the via holes being positioned directly below the pad structure.
    Type: Application
    Filed: August 25, 2009
    Publication date: December 24, 2009
    Applicant: IBIDEN CO., LTD.
    Inventors: Naohiro HIROSE, Hitoshi ITO, Yoshiyuki IWATA, Masanori KAWADE, Hajime YAZU
  • Publication number: 20090294979
    Abstract: There is provided a method of manufacturing a semiconductor substrate. The method includes: (a) forming a wiring pattern on a substrate; (b) covering the wiring pattern with an insulating resin, thereby forming a first insulating layer; (c) forming a second insulating layer on the first insulating layer; (d) forming a plurality of grooves through the second insulating layer; (e) forming at least one via hole through the first and second insulating layers by irradiating at least one of the grooves with a laser beam; (f) forming a seed metal layer on an inner surface of the at least one via hole, inner surfaces of the grooves, and a surface of the second insulating layer; and (g) forming a plating layer in the at least one via hole and the grooves, by an electrolytic plating using the seed metal layer as a power feeding layer.
    Type: Application
    Filed: May 26, 2009
    Publication date: December 3, 2009
    Applicant: Shinko Electric Industries Co., Ltd.
    Inventor: Hitoshi Ito