Patents by Inventor Hitoshi Kobayashi

Hitoshi Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250138101
    Abstract: A battery pack includes: an assembled battery in which power storage devices are connected; a current application line for applying current to the assembled battery; voltage detection lines for detecting voltages of the power storage devices; and a battery monitoring device that measures internal impedances of the power storage devices via the current application line and the voltage detection lines. Each of the power storage devices includes an electrode assembly in which a positive electrode plate and a negative electrode plate are alternately stacked, and an electrode plate on one principal surface of the electrode assembly and an electrode plate on the other principal surface of the electrode assembly have the same polarity, the direction of current that flows through the positive electrode plate is an opposite direction of the direction of current that flows through the negative electrode plate, and each of the power storage devices is stacked.
    Type: Application
    Filed: January 2, 2025
    Publication date: May 1, 2025
    Inventors: Susumu YOSHIKAWA, Hitoshi KOBAYASHI, Keiichi FUJII, Akira KAWABE
  • Patent number: 12273101
    Abstract: A semiconductor device includes a first transistor, a first drive circuit including a second transistor, and a second drive circuit including a third transistor. The second transistor and the third transistor are connected in series; and a connection node of the second and third transistors is connected to a gate electrode of the first transistor. The first transistor, the second transistor, and the third transistor are normally-off MOS HEMTs formed in a first substrate that includes GaN. The first drive circuit charges a parasitic capacitance of the first transistor. The second drive circuit discharges the parasitic capacitance of the first transistor.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: April 8, 2025
    Assignees: Kabusbiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Toru Sugiyama, Noriaki Yoshikawa, Yasuhiko Kuriyama, Akira Yoshioka, Hitoshi Kobayashi, Hung Hung, Yasuhiro Isobe, Tetsuya Ohno, Hideki Sekiguchi, Masaaki Onomura
  • Publication number: 20250079136
    Abstract: An object of the invention is to provide a plasma processing method for preventing generation of deposition from an underlying metal film and attaining an anisotropic shape in hard mask etching. The plasma processing method for forming a mask using a film to be etched whose underlying layer is a metal film according to the invention includes: a first step of etching, using a plasma generated by mixed gas containing O2 gas, CHF3 gas, NF3 gas, Ar gas, and He gas, while supplying pulse-modulated radio frequency power to a sample stage on which a sample having the film to be etched is placed; and a second step of etching while supplying continuous wave (CW) radio frequency power to the sample stage after the first step. The film to be etched is a TEOS film and a silicon nitride film, and the continuous wave (CW) radio frequency power is smaller than a product of the pulse-modulated radio frequency power and a pulse-modulated duty ratio and is smaller than 50 W.
    Type: Application
    Filed: April 11, 2022
    Publication date: March 6, 2025
    Inventors: Mai ISOMOTO, Hitoshi KOBAYASHI, Ryota TAKAHASHI, Satoshi UNE
  • Publication number: 20250055295
    Abstract: A BMS for managing a battery assembly includes: a BMU that manages the battery assembly; and a plurality of CMUs that monitor the battery assembly. One CMU among the plurality of CMUs includes a wireless communication circuit and a timer circuit, and based on a timing at which the timer circuit times out, repeatedly transitions between a first state in which the wireless communication circuit is supplied with power and therefore capable of receiving a wake-up signal transmitted by the BMU, and a second state in which the wireless communication circuit is not supplied with power.
    Type: Application
    Filed: October 23, 2024
    Publication date: February 13, 2025
    Inventors: Susumu YOSHIKAWA, Hitoshi KOBAYASHI, Keiichi FUJII, Akira KAWABE
  • Publication number: 20250055287
    Abstract: A BMS includes: a BMU that manages a battery assembly; and a plurality of CMUs that monitor the battery assembly. Among the plurality of CMUs, a first CMU includes a first wireless communication circuit and a first communication antenna for communicating with the BMU, and a second CMU includes a second wireless communication circuit and a second communication antenna for communicating with the BMU. The modulation scheme for wireless communication by the first wireless communication circuit is different from the modulation scheme for wireless communication by the second wireless communication circuit.
    Type: Application
    Filed: October 23, 2024
    Publication date: February 13, 2025
    Inventors: Susumu YOSHIKAWA, Hitoshi KOBAYASHI, Keiichi FUJII, Akira KAWABE
  • Publication number: 20250052824
    Abstract: A BMS for managing a battery assembly includes: a BMU that manages the battery assembly; a plurality of CMUs that monitor the battery assembly; and a setting circuit. The BMU wirelessly transmits, to the plurality of CMUs, a first signal including identification information of one CMU among the plurality of CMUs. Each of the plurality of CMUs includes identification information identifying itself, receives the first signal transmitted by the BMU, and outputs a second signal on condition that the first signal received matches the identification information. The setting circuit generates and outputs correspondence information that associates (i) position information of the one CMU, among the plurality of CMUs, that output the second signal with (ii) the identification information included in the first signal transmitted by the BMU.
    Type: Application
    Filed: October 24, 2024
    Publication date: February 13, 2025
    Inventors: Susumu YOSHIKAWA, Hitoshi KOBAYASHI, Keiichi FUJII, Akira KAWABE
  • Publication number: 20250055296
    Abstract: A BMS includes: a BMU that manages a battery assembly; a first CMU that monitors one or more battery cells included in the battery assembly; and a second CMU that monitors the one or more battery cells monitored by the first CMU. The first CMU includes a wireless communication circuit and a communication antenna for communicating with the BMU. The second cell monitoring circuit CMU includes a power line communication circuit, for communicating with the BMU, that uses a power line in the battery assembly.
    Type: Application
    Filed: October 24, 2024
    Publication date: February 13, 2025
    Inventors: Susumu YOSHIKAWA, Hitoshi KOBAYASHI, Keiichi FUJII, Akira KAWABE
  • Publication number: 20250046887
    Abstract: A BMS for managing a battery assembly includes: a BMU that manages the battery assembly and includes a communication antenna; and one or more CMUs that monitor the battery assembly and each include a communication antenna that communicates with the communication antenna. A communication antenna group including the communication antenna and one or more communication antennas is arranged in a straight line. The BMS further includes a conductor that covers at least part of the communication antenna group. The conductor includes a recess that extends in the alignment direction of the communication antenna group and is recessed in a direction away from the communication antenna group in a cross-section orthogonal to the alignment direction.
    Type: Application
    Filed: October 23, 2024
    Publication date: February 6, 2025
    Inventors: Susumu YOSHIKAWA, Hitoshi KOBAYASHI, Keiichi FUJII, Akira KAWABE
  • Patent number: 12190273
    Abstract: A work content analyzing apparatus of the present embodiment includes a first database storing state information indicating a state of each of one or a plurality of workers in association with time information and identification information of the worker, an estimation unit estimating the work content executed by the worker on the basis of at least two pieces of state information associated with same time in the state information stored in the first database, a specification unit specifying work time spent for the estimated work content on the basis of the state information stored in the first database and the time information associated with the state information, and an analysis unit analyzing the work content on the basis of the estimated work content and the specified work time.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: January 7, 2025
    Assignee: Toshiba Digital Solutions Corporation
    Inventors: Kazuki Yamamoto, Toshiyuki Morishita, Jun Takahashi, Hiroki Takenouchi, Ken Ishii, Hitoshi Kobayashi, Takashi Kusakabe, Yuto Akimoto
  • Publication number: 20240429476
    Abstract: A battery pack includes: a cell stack including secondary cells connected in series or parallel; a cell data calculator that calculates the SOC and the SOH of the secondary cells; and a first NFC unit that uses NFC to communicate with an external device regarding cell information related to the SOC and the SOH calculated by the cell data calculator.
    Type: Application
    Filed: September 3, 2024
    Publication date: December 26, 2024
    Inventors: Naoto AKUTSU, Hitoshi KOBAYASHI, Keiichi FUJII, Akira KAWABE
  • Publication number: 20240426929
    Abstract: A battery pack management system that manages a battery pack of storage batteries connected in series or parallel, includes: an acquisition unit (for example, a model parameter expander) that acquires respective impedances of the storage batteries corresponding to a first time point; and a generator (for example, an ID converter) that generates identification information of the battery pack based on the acquired impedances of the storage batteries.
    Type: Application
    Filed: September 3, 2024
    Publication date: December 26, 2024
    Inventors: Misaki MITSUOKA, Hitoshi KOBAYASHI, Keiichi FUJII, Akira KAWABE, Takumi KATO
  • Publication number: 20240418794
    Abstract: A battery monitoring device includes a measurement unit and a calculation unit. The measurement unit includes a voltage measurement unit and a current measurement unit. The calculation unit includes: storage that holds first relationship data indicating a relationship between SOC and OCV and second relationship data indicating a relationship between impedance and SOH; an impedance calculation unit that identifies a low current interval, sets a voltage obtained during the low current interval as a provisional OCV, and calculates an impedance of secondary cells from a voltage value and a current value in a transient current response; an SOH estimate unit that estimates an SOH by referencing the second relationship data using the impedance; and an SOC estimate unit that estimates an SOC by referencing the first relationship data based on the provisional OCV.
    Type: Application
    Filed: August 29, 2024
    Publication date: December 19, 2024
    Inventors: Tomohiro OKACHI, Hitoshi KOBAYASHI, Keiichi FUJII, Susumu YOSHIKAWA
  • Patent number: 12170316
    Abstract: A semiconductor device includes first and second nitride semiconductor layers. The second layer on the first nitride has a first region, a second region, and a third region between the first and second regions. A first gate electrode is in the first region and extends parallel to a surface of a substrate. A first source electrode is in the first region and extends in the first direction. A second gate electrode in the second region and extends in the first direction. A second source electrode is in the second region and extends in the first direction. A drain electrode coupled to a first and a second wiring. The first wiring directly contacts the second nitride semiconductor layer in the first region. The second wiring directly contacts the second nitride semiconductor layer in the second region. An insulation material is in the third region.
    Type: Grant
    Filed: October 20, 2023
    Date of Patent: December 17, 2024
    Assignees: Kabushika Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Akira Yoshioka, Yasuhiro Isobe, Hung Hung, Hitoshi Kobayashi, Tetsuya Ohno, Toru Sugiyama
  • Publication number: 20240410955
    Abstract: A battery pack includes: an assembled battery in which a plurality of batteries are connected; a current applying wire for applying an electric current to the assembled battery; a plurality of voltage detecting wires for detecting voltages of the plurality of batteries; and a battery monitoring device that measures internal impedances of the plurality of batteries. The battery monitoring device is located between a positive electrode-side battery terminal and a negative electrode-side battery terminal of each of the plurality of batteries that constitute the assembled battery. The plurality of voltage detecting wires are routed radially from the battery monitoring device.
    Type: Application
    Filed: August 22, 2024
    Publication date: December 12, 2024
    Inventors: Susumu YOSHIKAWA, Hitoshi KOBAYASHI, Keiichi FUJII, Akira KAWABE
  • Publication number: 20240377851
    Abstract: A semiconductor device includes: a lead frame; a first semiconductor chip mounted face-up above the lead frame; and a second semiconductor chip mounted face-down above the first semiconductor chip. The second semiconductor chip has a chip size smaller than a chip size of the first semiconductor chip. The second semiconductor chip includes a bandgap element (an NPN transistor, an N-parallel NPN transistor) including a positive-negative (PN) junction and included in a band gap reference circuit.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Satoshi ENDO, Takuya ISHII, Hitoshi KOBAYASHI, Kazuhito ITO, Shuichi OGATA
  • Publication number: 20240322027
    Abstract: A conductor layer is positioned between a gate electrode and a drain electrode. The conductor layer contacts a nitride semiconductor layer. The conductor layer is electrically connected with the drain electrode. The drain electrode includes a first part contacting the nitride semiconductor layer, and a second part positioned further toward the conductor layer side than the first part in a first direction. An insulating film includes a portion positioned between the conductor layer and the drain electrode. The second part is located on the portion of the insulating film.
    Type: Application
    Filed: August 23, 2023
    Publication date: September 26, 2024
    Inventors: Hitoshi KOBAYASHI, Masaaki ONOMURA, Toru SUGIYAMA, Akira YOSHIOKA, Yasuhiro ISOBE, Tetsuya OHNO, Hideki SEKIGUCHI, Hung HUNG, Yorito KAKIUCHI
  • Publication number: 20240321977
    Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, a conductive part, an insulating part, and a third electrode. The second semiconductor layer is located on the first semiconductor layer. The first electrode is located on the second semiconductor layer. The first electrode includes an electrode part and an electrode extension part. The electrode part contacts the second semiconductor layer. The electrode extension part extends from an upper end portion of the electrode part. The conductive part is positioned between the first electrode and the second electrode. The conductive part contacts an upper surface of the second semiconductor layer and contacting the first electrode. The insulating part is located on the conductive part and is positioned between the conductive part and the electrode extension part.
    Type: Application
    Filed: August 25, 2023
    Publication date: September 26, 2024
    Inventors: Akira YOSHIOKA, Hitoshi KOBAYASHI, Hideki SEKIGUCHI, Hung HUNG, Yasuhiro ISOBE, Toru SUGIYAMA
  • Patent number: 12100985
    Abstract: A BMS includes cell supervising circuits connected to an alternating current power line via a transformer, and a BMU connected to the alternating current power line via a transformer. The BMU includes a control microcomputer which instructs at least one of the cell supervising circuits to control the state of charge of a secondary battery cell monitored by the at least one of the cell supervising circuits, based on pieces of information in the cell supervising circuits, the pieces of information indicating states of charge of secondary battery cells monitored by the cell supervising circuits.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: September 24, 2024
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventor: Hitoshi Kobayashi
  • Patent number: 12074033
    Abstract: In a plasma processing method for plasma etching a silicon film or polysilicon film containing boron, the polysilicon film containing boron is etched by using a mixed gas of a halogen gas, a fluorine-containing gas, and a boron trichloride gas. According to plasma processing method, it is possible to improve the etching rate and reduce etching defects when plasma etching a silicon film or polysilicon film containing boron.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: August 27, 2024
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Chaomei Liu, Hitoshi Kobayashi, Masahito Mori, Ryota Takahashi
  • Patent number: 12062651
    Abstract: A semiconductor device according to an embodiment includes: a first nitride semiconductor layer having a first surface and a second surface; a first source electrode provided on the first surface; a first drain electrode provided on the first surface; a first gate electrode provided on the first surface between the first source electrode and the first drain electrode; a second nitride semiconductor layer having a third surface and a fourth surface, the third surface being provided on the second surface and facing the second surface, and the second nitride semiconductor layer having a smaller band gap than the first nitride semiconductor layer; and a first semiconductor device having a fifth surface provided on the fourth surface and facing the fourth surface with a size equal to or smaller than a size of the fourth surface, the first semiconductor device including a first semiconductor material having a smaller band gap than the second nitride semiconductor layer.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: August 13, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yasuhiro Isobe, Hung Hung, Akira Yoshioka, Toru Sugiyama, Hitoshi Kobayashi, Tetsuya Ohno, Masaaki Iwai, Naonori Hosokawa, Masaaki Onomura