Patents by Inventor Hitoshi Kobayashi

Hitoshi Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12027614
    Abstract: A semiconductor device of an embodiment includes: a semiconductor layer including an element region and an element isolation region; a first insulation film provided on the semiconductor layer; a first electrode provided on the first insulation film and extending in a first direction; a second electrode provided on the semiconductor layer, arranged in a second direction intersecting with the first direction, and extending in the first direction; a third electrode provided on the semiconductor layer, arranged in the second direction, and extending in the first direction; second insulation films provided between the first insulation film and the semiconductor layer, and interposing the third electrode in the second direction; a first field plate electrode provided on the first electrode and connected to the first electrode; a second field plate electrode provided on the first field plate electrode and connected to the second electrode; and a third field plate electrode provided on the third electrode and connec
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: July 2, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hitoshi Kobayashi, Yasuhiro Isobe, Hung Hung
  • Patent number: 12002858
    Abstract: A semiconductor device has a first and a second nitride semiconductor layer and a first and a second electrode thereon. A gate electrode is between the first and second electrodes. A gate field plate is on the gate electrode. A first field plate is above a position between the gate field plate and the second electrode. A second field plate is between the first field plate and the gate field plate. A distance from the first nitride semiconductor layer to the second field plate is shorter than a distance from the first nitride semiconductor layer to the portion of the gate field plate that protrudes the most towards the second electrode. The distance from the first nitride semiconductor layer to the second field plate is shorter than a distance from the first nitride semiconductor layer to an end surface of the first field plate on a first electrode side.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: June 4, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tetsuya Ohno, Akira Yoshioka, Toru Sugiyama, Hung Hung, Yasuhiro Isobe, Hitoshi Kobayashi
  • Publication number: 20240177574
    Abstract: The present disclosure relates to a medium processing apparatus, including: a banknote device configured to process a banknote, including a banknote device door arranged at an opening of a safe box and being movable between an open position and a closed position; a banknote device lock configured to switch the banknote device door between a locked state and an unlocked state; a loose coin device configured to process a loose coin, including a loose coin device door arranged at an opening of a safe box and being movable between an open position and a closed position; a loose coin device lock configured to switch the loose coin device door between a locked state and an unlocked state, wherein the banknote device lock and the loose coin device lock perform a switching between the locked state and the unlocked state independently from each other.
    Type: Application
    Filed: February 7, 2024
    Publication date: May 30, 2024
    Applicant: Glory Ltd.
    Inventors: Kazuhiko Takahashi, Takaaki Imoto, Hirofumi Tougo, Hitoshi Kobayashi
  • Patent number: 11965933
    Abstract: A battery monitoring device includes: a pair of terminals for measuring voltage or current of a battery, and to which a filter unit including a capacitive element is connected; an AD converter that measures a waveform of voltage between the terminals during charging or discharging of the capacitive element; and a time constant calculation unit that calculates a time constant of the filter unit based on the waveform measured. The AD converter is, for example, a first AD converter or a second AD converter. The filter unit is, for example, a first filter unit or a second filter unit.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: April 23, 2024
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Kazuo Matsukawa, Yu Okada, Yosuke Goto, Hitoshi Kobayashi, Keiichi Fujii
  • Publication number: 20240128981
    Abstract: An analog-to-digital conversion circuit includes: a first variable gain amplifier connected to an input terminal; a first AD converter connected to the first variable gain amplifier; a second variable gain amplifier connected to the input terminal; a second AD converter connected to the second variable gain amplifier; a selection circuit to which an output of the first AD converter and an output of the second AD converter are input, and which selects one of the outputs; and a control circuit that controls a gain change period of the first variable gain amplifier and a gain change period of the second variable gain amplifier in a relative manner.
    Type: Application
    Filed: December 21, 2023
    Publication date: April 18, 2024
    Inventor: Hitoshi KOBAYASHI
  • Publication number: 20240110992
    Abstract: A battery anomaly detection device includes: an alternating-current (AC) impedance measurer that measures AC impedance of a battery cell; and an anomaly determiner that determines whether the AC impedance is within a reference range, and when the AC impedance is not within the reference range, determines that the battery cell is an anomalous cell.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Akira KAWABE, Hitoshi KOBAYASHI, Keiichi FUJII
  • Patent number: 11948864
    Abstract: A semiconductor device has a first wiring extending in a first direction on a nitride semiconductor layer. A source electrode is electrically connected to the first wiring and extends in a second direction. A drain electrode extends in the second direction and includes a first and second portion extending in the second direction, spaced from each other in the first direction. An element isolation region is in the second nitride semiconductor layer between the first and second portions. A third portion extends in the second direction on the first and second portions. A gate electrode extends in the second direction on the second nitride semiconductor layer between the source electrode and the drain electrode. The portion includes holes therein aligned with each other along the second direction with the spacing between adjacent holes in the second direction increasing with increasing distance in the second direction from the first wiring.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: April 2, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Akira Yoshioka, Hung Hung, Yasuhiro Isobe, Toru Sugiyama, Hitoshi Kobayashi
  • Publication number: 20240105563
    Abstract: A semiconductor device includes a nitride semiconductor element, a first diode, and a second diode; the nitride semiconductor element includes a conductive mounting bed, a semiconductor substrate formed on the mounting bed, a first nitride semiconductor layer, a second nitride semiconductor layer, a first major electrode, a second major electrode, a first gate electrode, and a second gate electrode; the first diode includes a first anode electrode electrically connected to the mounting bed, and a first cathode electrode electrically connected to the first major electrode; and the second diode includes a second anode electrode electrically connected to the mounting bed, and a second cathode electrode electrically connected to the second major electrode.
    Type: Application
    Filed: March 9, 2023
    Publication date: March 28, 2024
    Inventors: Toru SUGIYAMA, Akira YOSHIOKA, Hitoshi KOBAYASHI, Hung HUNG, Yasuhiro ISOBE, Hideki SEKIGUCHI, Tetsuya OHNO, Masaaki ONOMURA
  • Publication number: 20240105826
    Abstract: A semiconductor device of an embodiment includes a semiconductor layer, a first insulating film provided on the semiconductor layer, a first electrode film provided on the first insulating film, a second electrode film provided on the first electrode film, and a first field plate electrode provided on the second electrode film. A lower end of the first field plate electrode is located on a second surface of the first electrode film, the second surface being in contact with the second electrode film, rather than a first surface of the first electrode film, the first surface being in contact with the first insulating film.
    Type: Application
    Filed: March 1, 2023
    Publication date: March 28, 2024
    Inventors: Hitoshi KOBAYASHI, Masaaki ONOMURA, Toru SUGIYAMA, Akira YOSHIOKA, Hung HUNG, Hideki SEKIGUCHI, Tetsuya OHNO, Yasuhiro ISOBE
  • Publication number: 20240094303
    Abstract: A battery state estimation device includes: a first state of charge (SOC) calculator that calculates a first SOC using a first method that uses the battery model parameter of a battery; a second SOC calculator that calculates a second SOC using a second method different from the first method; an alternating-current (AC) impedance measurement unit that measures the AC impedance of the battery when the error between the first SOC and the second SOC is greater than a predetermined threshold; and a battery model parameter calculator that calculates a battery model parameter using the measured AC impedance. The first SOC calculator recalculates the first SOC using the battery model parameter calculated.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Inventors: Keiichi FUJII, Hitoshi KOBAYASHI, Tomohiro OKACHI
  • Publication number: 20240097671
    Abstract: A semiconductor device includes a first transistor, a first drive circuit including a second transistor, and a second drive circuit including a third transistor. The second transistor and the third transistor are connected in series; and a connection node of the second and third transistors is connected to a gate electrode of the first transistor. The first transistor, the second transistor, and the third transistor are normally-off MOS HEMTs formed in a first substrate that includes GaN. The first drive circuit charges a parasitic capacitance of the first transistor. The second drive circuit discharges the parasitic capacitance of the first transistor.
    Type: Application
    Filed: February 10, 2023
    Publication date: March 21, 2024
    Inventors: Toru SUGIYAMA, Noriaki YOSHIKAWA, Yasuhiko KURIYAMA, Akira YOSHIOKA, Hitoshi KOBAYASHI, Hung HUNG, Yasuhiro ISOBE, Tetsuya OHNO, Hideki SEKIGUCHI, Masaaki ONOMURA
  • Patent number: 11933854
    Abstract: A battery management circuit includes: a reference signal generator that generates a first reference frequency signal and a second reference frequency signal having a phase different from a phase of the first reference frequency signal; an alternating-current superimposer that superimposes an alternating current on the secondary battery, the alternating current having a frequency component of the first reference frequency signal; a voltage measurer that measures a voltage of the secondary battery by performing sampling using a frequency; a current measurer that measures a current of the secondary battery by performing sampling using a frequency; and a converter that converts each of results of measurements by the voltage measurer and the current measurer into a complex voltage and a complex current, by multiplying the result of the measurement by the first reference frequency signal and the second reference frequency signal.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: March 19, 2024
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Yu Okada, Hitoshi Kobayashi, Keiichi Fujii
  • Publication number: 20240088280
    Abstract: According to one embodiment, a nitride semiconductor device includes a first semiconductor layer having a heterojunction, a second semiconductor layer on the first semiconductor layer and having another heterojunction, a drain electrode on the second semiconductor layer, a source electrode provided on the first semiconductor layer, a gate electrode provided on the first semiconductor layer between the drain electrode and the source electrode, and a first insulating film between the gate electrode and the drain electrode covering the first semiconductor layer and the second semiconductor layer. The second semiconductor layer being separated from the gate electrode by a portion of the insulating film. A distance from the second semiconductor layer to the gate electrode is shorter than a distance from the drain electrode to the gate electrode.
    Type: Application
    Filed: February 28, 2023
    Publication date: March 14, 2024
    Inventors: Hung HUNG, Yasuhiro ISOBE, Akira YOSHIOKA, Toru SUGIYAMA, Hitoshi KOBAYASHI
  • Patent number: 11928940
    Abstract: The present disclosure relates to a medium processing apparatus, including: a banknote device configured to process a banknote, including a banknote device door arranged at an opening of a safe box and being movable between an open position and a closed position; a banknote device lock configured to switch the banknote device door between a locked state and an unlocked state, a loose coin device configured to process a loose coin, including a loose coin device door arranged at an opening of a safe box and being movable between an open position and a closed position; a loose coin device lock configured to switch the loose coin device door between a locked state and an unlocked state, wherein the banknote device lock and the loose coin device lock perform a switching between the locked state and the unlocked state independently from each other.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: March 12, 2024
    Assignee: Glory Ltd.
    Inventors: Kazuhiko Takahashi, Takaaki Imoto, Hirofumi Tougo, Hitoshi Kobayashi
  • Publication number: 20240047533
    Abstract: A semiconductor device includes first and second nitride semiconductor layers. The second layer on the first nitride has a first region, a second region, and a third region between the first and second regions. A first gate electrode is in the first region and extends parallel to a surface of a substrate. A first source electrode is in the first region and extends in the first direction. A second gate electrode in the second region and extends in the first direction. A second source electrode is in the second region and extends in the first direction. A drain electrode coupled to a first and a second wiring. The first wiring directly contacts the second nitride semiconductor layer in the first region. The second wiring directly contacts the second nitride semiconductor layer in the second region. An insulation material is in the third region.
    Type: Application
    Filed: October 20, 2023
    Publication date: February 8, 2024
    Inventors: Akira YOSHIOKA, Yasuhiro ISOBE, Hung HUNG, Hitoshi KOBAYASHI, Tetsuya OHNO, Toru SUGIYAMA
  • Publication number: 20240007128
    Abstract: An analog-to-digital conversion circuit includes: a variable gain amplifier; a delta-sigma modulator that modulates an output of the variable gain amplifier to a pulse density modulation (PDM) signal; and a decimation filter that downsamples the PDM signal to output a first digital signal that is converted into a multi-bit digital signal. The decimation filter includes: a weight change unit that converts the PDM signal into a second digital signal that is weighted by multiplying a weight of the PDM signal by a reciprocal of an amplification factor of the variable gain amplifier; and a first digital filter that receives the second digital signal as an input, and outputs the first digital signal.
    Type: Application
    Filed: September 14, 2023
    Publication date: January 4, 2024
    Inventor: Hitoshi KOBAYASHI
  • Publication number: 20230402865
    Abstract: A cell stack management system includes a cell monitoring unit that measures an output voltage of a plurality of power storage cells, a battery management unit that manages a cell stack, and a first communication network that connects the cell monitoring unit and the battery management unit. The battery management unit includes: a first communication circuit connected to the first communication network; a second communication circuit connected to a second communication network for connecting to a higher-level system; a control circuit that controls the battery management unit; and a control circuit power supply. The cell stack management system includes a normal mode and a low-power mode as modes of operation. During transition from the low-power mode to the normal mode, the first communication circuit activates at least one of the control circuit power supply, the control circuit, or the second communication circuit.
    Type: Application
    Filed: August 28, 2023
    Publication date: December 14, 2023
    Inventors: Tsutomu SAKAKIBARA, Naohisa HATANI, Hitoshi KOBAYASHI, Jiro MIYAKE, Ken MARUYAMA, Toshinobu NAGASAWA, Toshiaki OZEKI, Goro MORI
  • Patent number: 11830916
    Abstract: A semiconductor device includes first and second nitride semiconductor layers. The second layer on the first nitride has a first region, a second region, and a third region between the first and second regions. A first gate electrode is in the first region and extends parallel to a surface of a substrate. A first source electrode is in the first region and extends in the first direction. A second gate electrode in the second region and extends in the first direction. A second source electrode is in the second region and extends in the first direction. A drain electrode coupled to a first and a second wiring. The first wiring directly contacts the second nitride semiconductor layer in the first region. The second wiring directly contacts the second nitride semiconductor layer in the second region. An insulation material is in the third region.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: November 28, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Akira Yoshioka, Yasuhiro Isobe, Hung Hung, Hitoshi Kobayashi, Tetsuya Ohno, Toru Sugiyama
  • Patent number: 11824390
    Abstract: A battery control system is provided with battery monitoring control circuits for measuring an output voltage of an individual or secondary battery cells, which are connected in an assembled battery divided into blocks; and a control circuit for controlling the battery monitoring control circuits. Each of the batter monitoring control circuits includes a communication interface for communications between the battery monitoring control circuits or communications with the control circuit; a power converter for converting a start-up signal into a DC voltage; and a start-up circuit that receives the DC voltage and generates a start-up control signal for starting the battery monitoring control circuit.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: November 21, 2023
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventor: Hitoshi Kobayashi
  • Publication number: 20230290871
    Abstract: A semiconductor device includes: a drain electrode including a plurality of drain finger parts; a source electrode including a plurality of source finger parts and a Kelvin source part electrically connected with the source finger parts; a sense electrode positioned between a drain finger part and the Kelvin source part, which are next to each other in a particular direction; and a gate electrode positioned between a drain finger part and a source finger part, which are next to each other in the particular direction, and between a drain finger part and the sense electrode, which are next to each other in the particular direction. The sense electrode and the Kelvin source part are electrically connected via a sense resistance due to a spacing between the sense electrode and the Kelvin source part in the particular direction.
    Type: Application
    Filed: September 12, 2022
    Publication date: September 14, 2023
    Inventors: Toru SUGIYAMA, Akira YOSHIOKA, Hitoshi KOBAYASHI, Masaaki ONOMURA, Yasuhiro ISOBE, Hung HUNG, Hideki SEKIGUCHI, Tetsuya OHNO