Patents by Inventor Hitoshi Mitani

Hitoshi Mitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190170586
    Abstract: There is provided an imaging device including: an imaging section including pixels that generate pixel signals on the basis of incident light, the pixels including a polarization pixel having a predetermined polarization direction and a non-polarization pixel; and a polarization rotating section provided on an incidence plane side of the imaging section, and configured to rotate a polarization direction of the incident light.
    Type: Application
    Filed: August 9, 2017
    Publication date: June 6, 2019
    Inventors: Hitoshi MITANI, Masafumi WAKAZONO
  • Publication number: 20150150516
    Abstract: The biological information processing system includes a basal heart rate information acquisition section that acquires basal heart rate information that represents the heart rate in a deep sleep state, a heart rate information acquisition section that acquires heart rate information, and a health condition information calculation section that calculates health condition information that represents a health condition based on relative information about the basal heart rate information and the heart rate information.
    Type: Application
    Filed: February 10, 2015
    Publication date: June 4, 2015
    Inventors: Osamu Tochikubo, Naoshi Furuta, Hitoshi Mitani
  • Patent number: 8098324
    Abstract: An imaging device includes an imaging unit configured to execute processing to capture image data, a global positioning system (GPS) device configured to execute position calculation processing based on data received from a satellite, and a main controller configured to measure an imaging frequency of the imaging unit, to determine or update a control parameter as a condition for a transition of an operation state of the GPS device based on the measured imaging frequency, and to cause a transition of the operation state of the GPS device based on the determined or updated control parameter.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: January 17, 2012
    Assignee: Sony Corporation
    Inventors: Ichiro Ueno, Hitoshi Mitani, Baiping Liao
  • Patent number: 8068699
    Abstract: An imaging apparatus includes imaging means for imaging an image at a first aspect ratio, and image processing means for converting an original image at the first aspect ratio, which is imaged by the imaging means, to a converted image at a second aspect ratio, which is different from the first aspect ratio, by discarding a section of the original image as a discard section, and creating the converted image by, if the selected magnification of the converted image is lower than that of the original image, reducing the size of the original image according to the magnification and then adding a margin to the reduced original image and discarding the discard section according to the magnification as necessary.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: November 29, 2011
    Assignee: Sony Corporation
    Inventor: Hitoshi Mitani
  • Patent number: 7948063
    Abstract: Semiconductor devices required forming a stress control film to handle different stresses on each side when optimizing the stress on the respective P channel and N channel sections. A unique feature of the semiconductor device of this invention is that P and N channel stress are respectively optimized by making use of a stress control film jointly for the P and N channels that conveys stress in different directions by utilizing the film thickness.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: May 24, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hitoshi Mitani
  • Publication number: 20110050891
    Abstract: An imaging device includes an imaging unit configured to execute processing to capture image data, a global positioning system (GPS) device configured to execute position calculation processing based on data received from a satellite, and a main controller configured to measure an imaging frequency of the imaging unit, to determine or update a control parameter as a condition for a transition of an operation state of the GPS device based on the measured imaging frequency, and to cause a transition of the operation state of the GPS device based on the determined or updated control parameter.
    Type: Application
    Filed: November 5, 2010
    Publication date: March 3, 2011
    Applicant: SONY CORPORATION
    Inventors: Ichiro Ueno, Hitoshi Mitani, Baiping Liao
  • Patent number: 7875954
    Abstract: Provided is a semiconductor chip (1) including: at least one fuse element (21); a fuse opening (17) formed above the fuse element (21); and a discharge electrode (31) that is formed below a bottom portion (17a) of the fuse opening (17), and is formed in one of the same layer with the fuse element (21) and the above layer of the fuse element (21). Accordingly, the current caused to flow due to the electrostatic discharge generated at the time of assembling the semiconductor chip can be discharged through the discharge electrode (31). As a result, the current caused to flow due to the electrostatic discharge generated at the time of assembling the semiconductor chip can be prevented from being discharged through the fuse element, whereby a problem in that a functional failure occurs in the semiconductor chip can be solved.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: January 25, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hitoshi Mitani
  • Patent number: 7843506
    Abstract: An imaging device includes an imaging unit configured to execute processing to capture image data, a global positioning system (GPS) device configured to execute position calculation processing based on data received from a satellite, and a main controller configured to measure an imaging frequency of the imaging unit, to determine or update a control parameter as a condition for a transition of an operation state of the GPS device based on the measured imaging frequency, and to cause a transition of the operation state of the GPS device based on the determined or updated control parameter.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: November 30, 2010
    Assignee: Sony Corporation
    Inventors: Ichiro Ueno, Hitoshi Mitani, Baiping Liao
  • Patent number: 7745936
    Abstract: A semiconductor integrated circuit device includes a substrate having a PROM formed thereon in which the data memory state of the PROM is changed by the irradiation of light, and a multilayer wiring structure formed on the same side of the substrate as the PROM is formed. The multilayer wiring structure includes a transparent area, a shield area, and a PAD portion. The transparent area is formed from transparent material at a position opposite to the PROM area where the PROM is formed, and used as a light guiding path from the outside of the multilayer wiring structure to the PROM. The shield area is formed continuously from shielding materials arranged in several layers in the periphery of the transparent area. The PAD portion is formed on the outside of the shield area in regard to the transparent area, and controls the memory state of the PROM.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: June 29, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hitoshi Mitani
  • Publication number: 20090206410
    Abstract: Semiconductor devices required forming a stress control film to handle different stresses on each side when optimizing the stress on the respective P channel and N channel sections. A unique feature of the semiconductor device of this invention is that P and N channel stress are respectively optimized by making use of a stress control film jointly for the P and N channels that conveys stress in different directions by utilizing the film thickness.
    Type: Application
    Filed: January 21, 2009
    Publication date: August 20, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Hitoshi Mitani
  • Publication number: 20090001497
    Abstract: A semiconductor integrated circuit device includes a substrate having a PROM formed thereon in which the data memory state of the PROM is changed by the irradiation of light, and a multilayer wiring structure formed on the same side of the substrate as the PROM is formed. The multilayer wiring structure includes a transparent area, a shield area, and a PAD portion. The transparent area is formed from transparent material at a position opposite to the PROM area where the PROM is formed, and used as a light guiding path from the outside of the multilayer wiring structure to the PROM. The shield area is formed continuously from shielding materials arranged in several layers in the periphery of the transparent area. The PAD portion is formed on the outside of the shield area in regard to the transparent area, and controls the memory state of the PROM.
    Type: Application
    Filed: June 30, 2008
    Publication date: January 1, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Hitoshi MITANI
  • Publication number: 20080193047
    Abstract: An imaging apparatus includes imaging means for imaging an image at a first aspect ratio, and image processing means for converting an original image at the first aspect ratio, which is imaged by the imaging means, to a converted image at a second aspect ratio, which is different from the first aspect ratio, by discarding a section of the original image as a discard section, and creating the converted image by, if the selected magnification of the converted image is lower than that of the original image, reducing the size of the original image according to the magnification and then adding a margin to the reduced original image and discarding the discard section according to the magnification as necessary.
    Type: Application
    Filed: February 6, 2008
    Publication date: August 14, 2008
    Applicant: Sony Corporation
    Inventor: Hitoshi Mitani
  • Publication number: 20080142922
    Abstract: Provided is a semiconductor chip (1) including: at least one fuse element (21); a fuse opening (17) formed above the fuse element (21); and a discharge electrode (31) that is formed below a bottom portion (17a) of the fuse opening (17), and is formed in one of the same layer with the fuse element (21) and the above layer of the fuse element (21). Accordingly, the current caused to flow due to the electrostatic discharge generated at the time of assembling the semiconductor chip can be discharged through the discharge electrode (31). As a result, the current caused to flow due to the electrostatic discharge generated at the time of assembling the semiconductor chip can be prevented from being discharged through the fuse element, whereby a problem in that a functional failure occurs in the semiconductor chip can be solved.
    Type: Application
    Filed: December 13, 2007
    Publication date: June 19, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Hitoshi Mitani
  • Publication number: 20070263981
    Abstract: An imaging device includes an imaging unit configured to execute processing to capture image data, a global positioning system (GPS) device configured to execute position calculation processing based on data received from a satellite, and a main controller configured to measure an imaging frequency of the imaging unit, to determine or update a control parameter as a condition for a transition of an operation state of the GPS device based on the measured imaging frequency, and to cause a transition of the operation state of the GPS device based on the determined or updated control parameter.
    Type: Application
    Filed: December 4, 2006
    Publication date: November 15, 2007
    Applicant: Sony Corporation
    Inventors: Ichiro Ueno, Hitoshi Mitani, Baiping Liao
  • Patent number: 6466233
    Abstract: An information processing unit controls a plurality of electronic devices. The information processing unit includes a storage unit for storing input graphical-user-interface data on the electronic devices, a display unit for displaying graphical user interfaces corresponding to the graphical-user-interface data stored in the storage unit, a detecting unit for detecting user operations corresponding to the graphical user interfaces displayed on the display unit, and a transmitting unit for transmitting control signals controlling the electronic devices in accordance with the results of detection by the detecting unit.
    Type: Grant
    Filed: November 19, 1999
    Date of Patent: October 15, 2002
    Assignee: Sony Corporation
    Inventor: Hitoshi Mitani
  • Patent number: 6031291
    Abstract: A semiconductor device having a semiconductor substrate, an impurity diffused layer formed in a principal surface of the semiconductor substrate, a conductive member formed on the semiconductor substrate adjacent to the impurity diffused layer and having a sloped surface inclined to the principal surface of the semiconductor substrate, an insulator film deposited to cover the impurity diffused layer and the conductive member, and a common contact hole formed through the insulator film to extend over a surface of the impurity diffused layer and the sloped surface of the conductive member.
    Type: Grant
    Filed: October 30, 1995
    Date of Patent: February 29, 2000
    Assignee: NEC Corporation
    Inventors: Norifumi Sato, Takami Hiruma, Hitoshi Mitani, Hidetaka Natsume
  • Patent number: 5949113
    Abstract: A static RAM has a low resistive contact film disposed in direct contact with a storage node of a memory cell and the gate electrode of a driver transistor in a through-hole, and in direct contact with an end portion of a high-resistance load. An accurate and stable resistance can be obtained for the high-resistance load without raising the contact resistance between the storage node and the gate electrode of the driver transistor.
    Type: Grant
    Filed: February 18, 1998
    Date of Patent: September 7, 1999
    Assignee: NEC Corporation
    Inventors: Noriyuki Ota, Shingo Hashimoto, Hitoshi Mitani
  • Patent number: 5895238
    Abstract: A method for manufacturing a semiconductor device having impurity doped regions serving as source and drain and a semiconductor device obtained by the application of the same method are disclosed. In the method, a semiconductor substrate having a gate oxide is prepared, and a gate electrode is formed on the gate oxide. A first dielectric film is formed on the semiconductor substrate impurity ions of a first conductive type into the semiconductor substrate while permitting the gate electrode and the first dielectric film formed on the side walls of the gate electrode to serve as self-aligning masks. Then, a second dielectric film to be deposited on the first dielectric film, and an anisotropic etching is effected on at least on the second dielectric film to form on the side walls of the gate electrode spacers having a prescribed profile.
    Type: Grant
    Filed: December 9, 1997
    Date of Patent: April 20, 1999
    Assignee: NEC Corporation
    Inventor: Hitoshi Mitani
  • Patent number: 5770495
    Abstract: The invention provides a method of fabricating a semiconductor device, including the steps of (a) forming an impurity region at a surface of a silicon substrate, (b) depositing an insulative film over the silicon substrate, (c) forming a contact hole through the insulative film to expose the impurity region of the silicon substrate, (d) forming an electrode wiring over the contact hole, the electrode wiring comprising a refractory metal silicide film and a silicon film overlying on the metal silicide film, the metal silicide film overlying the exposed impurity region, (e) depositing a second insulative film over a resultant, (f) depositing a polysilicon film on the second insulative film, (g) patterning the polysilicon film to form an element, and (h) heat-treating a resultant at high temperature in oxidizing atmosphere. The step (h) is to be carried out at any time after the step (f) has been completed.
    Type: Grant
    Filed: October 26, 1995
    Date of Patent: June 23, 1998
    Assignee: NEC Corporation
    Inventors: Nolifumi Sato, Shinji Ohara, Hitoshi Mitani, Hidetaka Natsume, Takami Hiruma
  • Patent number: 5761113
    Abstract: In an SRAM cell including two cross-coupled inverters each having a first resistance element and a drive MOS transistor, a second resistance element is connected between the first and the drive MOS transistor. A gate electrode of the drive MOS transistor of one of the inverters is connected between the first and second resistance elements of the other.
    Type: Grant
    Filed: October 30, 1995
    Date of Patent: June 2, 1998
    Assignee: NEC Corporation
    Inventors: Hidetaka Natsume, Nolifumi Sato, Hitoshi Mitani, Takami Hiruma