Patents by Inventor Hitoshi Mitani
Hitoshi Mitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20190170586Abstract: There is provided an imaging device including: an imaging section including pixels that generate pixel signals on the basis of incident light, the pixels including a polarization pixel having a predetermined polarization direction and a non-polarization pixel; and a polarization rotating section provided on an incidence plane side of the imaging section, and configured to rotate a polarization direction of the incident light.Type: ApplicationFiled: August 9, 2017Publication date: June 6, 2019Inventors: Hitoshi MITANI, Masafumi WAKAZONO
-
Publication number: 20150150516Abstract: The biological information processing system includes a basal heart rate information acquisition section that acquires basal heart rate information that represents the heart rate in a deep sleep state, a heart rate information acquisition section that acquires heart rate information, and a health condition information calculation section that calculates health condition information that represents a health condition based on relative information about the basal heart rate information and the heart rate information.Type: ApplicationFiled: February 10, 2015Publication date: June 4, 2015Inventors: Osamu Tochikubo, Naoshi Furuta, Hitoshi Mitani
-
Patent number: 8098324Abstract: An imaging device includes an imaging unit configured to execute processing to capture image data, a global positioning system (GPS) device configured to execute position calculation processing based on data received from a satellite, and a main controller configured to measure an imaging frequency of the imaging unit, to determine or update a control parameter as a condition for a transition of an operation state of the GPS device based on the measured imaging frequency, and to cause a transition of the operation state of the GPS device based on the determined or updated control parameter.Type: GrantFiled: November 5, 2010Date of Patent: January 17, 2012Assignee: Sony CorporationInventors: Ichiro Ueno, Hitoshi Mitani, Baiping Liao
-
Patent number: 8068699Abstract: An imaging apparatus includes imaging means for imaging an image at a first aspect ratio, and image processing means for converting an original image at the first aspect ratio, which is imaged by the imaging means, to a converted image at a second aspect ratio, which is different from the first aspect ratio, by discarding a section of the original image as a discard section, and creating the converted image by, if the selected magnification of the converted image is lower than that of the original image, reducing the size of the original image according to the magnification and then adding a margin to the reduced original image and discarding the discard section according to the magnification as necessary.Type: GrantFiled: February 6, 2008Date of Patent: November 29, 2011Assignee: Sony CorporationInventor: Hitoshi Mitani
-
Patent number: 7948063Abstract: Semiconductor devices required forming a stress control film to handle different stresses on each side when optimizing the stress on the respective P channel and N channel sections. A unique feature of the semiconductor device of this invention is that P and N channel stress are respectively optimized by making use of a stress control film jointly for the P and N channels that conveys stress in different directions by utilizing the film thickness.Type: GrantFiled: January 21, 2009Date of Patent: May 24, 2011Assignee: Renesas Electronics CorporationInventor: Hitoshi Mitani
-
Publication number: 20110050891Abstract: An imaging device includes an imaging unit configured to execute processing to capture image data, a global positioning system (GPS) device configured to execute position calculation processing based on data received from a satellite, and a main controller configured to measure an imaging frequency of the imaging unit, to determine or update a control parameter as a condition for a transition of an operation state of the GPS device based on the measured imaging frequency, and to cause a transition of the operation state of the GPS device based on the determined or updated control parameter.Type: ApplicationFiled: November 5, 2010Publication date: March 3, 2011Applicant: SONY CORPORATIONInventors: Ichiro Ueno, Hitoshi Mitani, Baiping Liao
-
Patent number: 7875954Abstract: Provided is a semiconductor chip (1) including: at least one fuse element (21); a fuse opening (17) formed above the fuse element (21); and a discharge electrode (31) that is formed below a bottom portion (17a) of the fuse opening (17), and is formed in one of the same layer with the fuse element (21) and the above layer of the fuse element (21). Accordingly, the current caused to flow due to the electrostatic discharge generated at the time of assembling the semiconductor chip can be discharged through the discharge electrode (31). As a result, the current caused to flow due to the electrostatic discharge generated at the time of assembling the semiconductor chip can be prevented from being discharged through the fuse element, whereby a problem in that a functional failure occurs in the semiconductor chip can be solved.Type: GrantFiled: December 13, 2007Date of Patent: January 25, 2011Assignee: Renesas Electronics CorporationInventor: Hitoshi Mitani
-
Patent number: 7843506Abstract: An imaging device includes an imaging unit configured to execute processing to capture image data, a global positioning system (GPS) device configured to execute position calculation processing based on data received from a satellite, and a main controller configured to measure an imaging frequency of the imaging unit, to determine or update a control parameter as a condition for a transition of an operation state of the GPS device based on the measured imaging frequency, and to cause a transition of the operation state of the GPS device based on the determined or updated control parameter.Type: GrantFiled: December 4, 2006Date of Patent: November 30, 2010Assignee: Sony CorporationInventors: Ichiro Ueno, Hitoshi Mitani, Baiping Liao
-
Patent number: 7745936Abstract: A semiconductor integrated circuit device includes a substrate having a PROM formed thereon in which the data memory state of the PROM is changed by the irradiation of light, and a multilayer wiring structure formed on the same side of the substrate as the PROM is formed. The multilayer wiring structure includes a transparent area, a shield area, and a PAD portion. The transparent area is formed from transparent material at a position opposite to the PROM area where the PROM is formed, and used as a light guiding path from the outside of the multilayer wiring structure to the PROM. The shield area is formed continuously from shielding materials arranged in several layers in the periphery of the transparent area. The PAD portion is formed on the outside of the shield area in regard to the transparent area, and controls the memory state of the PROM.Type: GrantFiled: June 30, 2008Date of Patent: June 29, 2010Assignee: NEC Electronics CorporationInventor: Hitoshi Mitani
-
Publication number: 20090206410Abstract: Semiconductor devices required forming a stress control film to handle different stresses on each side when optimizing the stress on the respective P channel and N channel sections. A unique feature of the semiconductor device of this invention is that P and N channel stress are respectively optimized by making use of a stress control film jointly for the P and N channels that conveys stress in different directions by utilizing the film thickness.Type: ApplicationFiled: January 21, 2009Publication date: August 20, 2009Applicant: NEC Electronics CorporationInventor: Hitoshi Mitani
-
Publication number: 20090001497Abstract: A semiconductor integrated circuit device includes a substrate having a PROM formed thereon in which the data memory state of the PROM is changed by the irradiation of light, and a multilayer wiring structure formed on the same side of the substrate as the PROM is formed. The multilayer wiring structure includes a transparent area, a shield area, and a PAD portion. The transparent area is formed from transparent material at a position opposite to the PROM area where the PROM is formed, and used as a light guiding path from the outside of the multilayer wiring structure to the PROM. The shield area is formed continuously from shielding materials arranged in several layers in the periphery of the transparent area. The PAD portion is formed on the outside of the shield area in regard to the transparent area, and controls the memory state of the PROM.Type: ApplicationFiled: June 30, 2008Publication date: January 1, 2009Applicant: NEC ELECTRONICS CORPORATIONInventor: Hitoshi MITANI
-
Publication number: 20080193047Abstract: An imaging apparatus includes imaging means for imaging an image at a first aspect ratio, and image processing means for converting an original image at the first aspect ratio, which is imaged by the imaging means, to a converted image at a second aspect ratio, which is different from the first aspect ratio, by discarding a section of the original image as a discard section, and creating the converted image by, if the selected magnification of the converted image is lower than that of the original image, reducing the size of the original image according to the magnification and then adding a margin to the reduced original image and discarding the discard section according to the magnification as necessary.Type: ApplicationFiled: February 6, 2008Publication date: August 14, 2008Applicant: Sony CorporationInventor: Hitoshi Mitani
-
Publication number: 20080142922Abstract: Provided is a semiconductor chip (1) including: at least one fuse element (21); a fuse opening (17) formed above the fuse element (21); and a discharge electrode (31) that is formed below a bottom portion (17a) of the fuse opening (17), and is formed in one of the same layer with the fuse element (21) and the above layer of the fuse element (21). Accordingly, the current caused to flow due to the electrostatic discharge generated at the time of assembling the semiconductor chip can be discharged through the discharge electrode (31). As a result, the current caused to flow due to the electrostatic discharge generated at the time of assembling the semiconductor chip can be prevented from being discharged through the fuse element, whereby a problem in that a functional failure occurs in the semiconductor chip can be solved.Type: ApplicationFiled: December 13, 2007Publication date: June 19, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Hitoshi Mitani
-
Publication number: 20070263981Abstract: An imaging device includes an imaging unit configured to execute processing to capture image data, a global positioning system (GPS) device configured to execute position calculation processing based on data received from a satellite, and a main controller configured to measure an imaging frequency of the imaging unit, to determine or update a control parameter as a condition for a transition of an operation state of the GPS device based on the measured imaging frequency, and to cause a transition of the operation state of the GPS device based on the determined or updated control parameter.Type: ApplicationFiled: December 4, 2006Publication date: November 15, 2007Applicant: Sony CorporationInventors: Ichiro Ueno, Hitoshi Mitani, Baiping Liao
-
Patent number: 6466233Abstract: An information processing unit controls a plurality of electronic devices. The information processing unit includes a storage unit for storing input graphical-user-interface data on the electronic devices, a display unit for displaying graphical user interfaces corresponding to the graphical-user-interface data stored in the storage unit, a detecting unit for detecting user operations corresponding to the graphical user interfaces displayed on the display unit, and a transmitting unit for transmitting control signals controlling the electronic devices in accordance with the results of detection by the detecting unit.Type: GrantFiled: November 19, 1999Date of Patent: October 15, 2002Assignee: Sony CorporationInventor: Hitoshi Mitani
-
Patent number: 6031291Abstract: A semiconductor device having a semiconductor substrate, an impurity diffused layer formed in a principal surface of the semiconductor substrate, a conductive member formed on the semiconductor substrate adjacent to the impurity diffused layer and having a sloped surface inclined to the principal surface of the semiconductor substrate, an insulator film deposited to cover the impurity diffused layer and the conductive member, and a common contact hole formed through the insulator film to extend over a surface of the impurity diffused layer and the sloped surface of the conductive member.Type: GrantFiled: October 30, 1995Date of Patent: February 29, 2000Assignee: NEC CorporationInventors: Norifumi Sato, Takami Hiruma, Hitoshi Mitani, Hidetaka Natsume
-
Patent number: 5949113Abstract: A static RAM has a low resistive contact film disposed in direct contact with a storage node of a memory cell and the gate electrode of a driver transistor in a through-hole, and in direct contact with an end portion of a high-resistance load. An accurate and stable resistance can be obtained for the high-resistance load without raising the contact resistance between the storage node and the gate electrode of the driver transistor.Type: GrantFiled: February 18, 1998Date of Patent: September 7, 1999Assignee: NEC CorporationInventors: Noriyuki Ota, Shingo Hashimoto, Hitoshi Mitani
-
Patent number: 5895238Abstract: A method for manufacturing a semiconductor device having impurity doped regions serving as source and drain and a semiconductor device obtained by the application of the same method are disclosed. In the method, a semiconductor substrate having a gate oxide is prepared, and a gate electrode is formed on the gate oxide. A first dielectric film is formed on the semiconductor substrate impurity ions of a first conductive type into the semiconductor substrate while permitting the gate electrode and the first dielectric film formed on the side walls of the gate electrode to serve as self-aligning masks. Then, a second dielectric film to be deposited on the first dielectric film, and an anisotropic etching is effected on at least on the second dielectric film to form on the side walls of the gate electrode spacers having a prescribed profile.Type: GrantFiled: December 9, 1997Date of Patent: April 20, 1999Assignee: NEC CorporationInventor: Hitoshi Mitani
-
Patent number: 5770495Abstract: The invention provides a method of fabricating a semiconductor device, including the steps of (a) forming an impurity region at a surface of a silicon substrate, (b) depositing an insulative film over the silicon substrate, (c) forming a contact hole through the insulative film to expose the impurity region of the silicon substrate, (d) forming an electrode wiring over the contact hole, the electrode wiring comprising a refractory metal silicide film and a silicon film overlying on the metal silicide film, the metal silicide film overlying the exposed impurity region, (e) depositing a second insulative film over a resultant, (f) depositing a polysilicon film on the second insulative film, (g) patterning the polysilicon film to form an element, and (h) heat-treating a resultant at high temperature in oxidizing atmosphere. The step (h) is to be carried out at any time after the step (f) has been completed.Type: GrantFiled: October 26, 1995Date of Patent: June 23, 1998Assignee: NEC CorporationInventors: Nolifumi Sato, Shinji Ohara, Hitoshi Mitani, Hidetaka Natsume, Takami Hiruma
-
Patent number: 5761113Abstract: In an SRAM cell including two cross-coupled inverters each having a first resistance element and a drive MOS transistor, a second resistance element is connected between the first and the drive MOS transistor. A gate electrode of the drive MOS transistor of one of the inverters is connected between the first and second resistance elements of the other.Type: GrantFiled: October 30, 1995Date of Patent: June 2, 1998Assignee: NEC CorporationInventors: Hidetaka Natsume, Nolifumi Sato, Hitoshi Mitani, Takami Hiruma