Patents by Inventor Hitoshi Ninomiya

Hitoshi Ninomiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080197381
    Abstract: A semiconductor device is provided with a vertical MOSFET including an N-type drift region that has a {110} crystal plane serving as the main surface thereof, a trench gate structure formed in a trench that has a {100} crystal plane serving as a sidewall surface thereof, and plural P-type column region structures provided in the N-type drift region 3, making up the super-junction structure. The P-type column region structures are disposed so as to be separated from each other in a plan view, and each of the plurality of column structures includes a plurality of column regions of the second conductivity type separated from each other in a cross-sectional view. By applying ion implantation of a P-type dopant to the main surface from a direction vertical to the main surface, the P-type column regions are formed down to sufficiently deeper positions in the drift region due to channeling. By so doing, it is possible to obtain a semiconductor device with an enhanced breakdown voltage.
    Type: Application
    Filed: February 12, 2008
    Publication date: August 21, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yoshiya Kawashima, Yoshinao Miura, Hitoshi Ninomiya
  • Publication number: 20080076223
    Abstract: A semiconductor device 100 includes an element-forming region having gate electrode 108 formed therein, and a circumferential region formed in the outer circumference of the element-forming region and having an element-isolating region 118 formed therein. On the main surface of the semiconductor substrate 101, there is formed a parallel pn layer having an N-type drift region 104 and P-type column regions 106 alternately arranged therein. In the circumferential region, there is formed a field electrode 120, but the field electrode 120 is not formed on the P-type column regions 106. The P-type column regions 106 in the circumferential region are formed with a depth larger than or equal to that of the P-type column regions 106 in the element-forming region.
    Type: Application
    Filed: November 21, 2007
    Publication date: March 27, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Hitoshi Ninomiya, Yoshinao Miura
  • Patent number: 7335949
    Abstract: A semiconductor device 100 includes an element-forming region having gate electrode 108 formed therein, and a circumferential region formed in the outer circumference of the element-forming region and having an element-isolating region 118 formed therein. On the main surface of the semiconductor substrate 101, there is formed a parallel pn layer having an N-type drift region 104 and P-type column regions 106 alternately arranged therein. In the circumferential region, there is formed a field electrode 120, but the field electrode 120 is not formed on the P-type column regions 106. The P-type column regions 106 in the circumferential region are formed with a depth larger than or equal to that of the P-type column regions 106 in the element-forming region.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: February 26, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Hitoshi Ninomiya, Yoshinao Miura
  • Publication number: 20080032477
    Abstract: A semiconductor device comprises a drift region of a first conduction type, a base region of a second conduction type, a source region of the first conduction type, a contact hole, a column region of the second conduction type, a plug and wiring. The drift region formed on a semiconductor substrate of the first conduction type. The base region of a second is formed in a prescribed region of the surface of the drift region. The source region is formed in a prescribed region of the surface of the base region. The contact hole extends from the source region surface side to the base region. The column region is formed in the drift region below the contact hole. The plug comprises a first conductive material and fills the contact hole. The wiring comprises a second conductive material and is electrically connected to the plug.
    Type: Application
    Filed: September 26, 2007
    Publication date: February 7, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Hitoshi Ninomiya
  • Patent number: 7307310
    Abstract: A semiconductor device comprises a drift region of a first conduction type, a base region of a second conduction type, a source region of the first conduction type, a contact hole, a column region of the second conduction type, a plug and wiring. The drift region formed on a semiconductor substrate of the first conduction type. The base region of a second is formed in a prescribed region of the surface of the drift region. The source region is formed in a prescribed region of the surface of the base region. The contact hole extends from the source region surface side to the base region. The column region is formed in the drift region below the contact hole. The plug comprises a first conductive material and fills the contact hole. The wiring comprises a second conductive material and is electrically connected to the plug.
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: December 11, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Hitoshi Ninomiya
  • Patent number: 7279747
    Abstract: A semiconductor device includes a first conductivity type semiconductor substrate. A first conductivity type drift layer is formed on a surface of the first conductivity type semiconductor substrate, and a second conductivity type base region is produced in the first conductivity type drift layer. The second conductivity type base region has a trench formed in a surface thereof. A trench-stuffed layer is formed by stuffing the trench with a suitable material, and a second conductivity type column region formed in the first conductivity type drift layer and sited beneath the trench-stuffed layer.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: October 9, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Hitoshi Ninomiya
  • Publication number: 20070138550
    Abstract: Semiconductor device exhibiting higher breakdown voltage and method for manufacturing the same. A power MOSFET includes: a p-type first base region; a p-type second base region, formed in the first base region and containing a higher impurity concentration than the first base region; and an n-type source region, formed in first base region and joined to the first base region and the second base region, and placed in a position that is shallower than the second base region, a portion of the source region being provided on the second base region. The source region includes first source region that joins the first base region and a second source region that is continually provided in first source region and formed on the second base region. A joined surface of the second source region with the second base region is expanded to a side of the second source region.
    Type: Application
    Filed: December 13, 2006
    Publication date: June 21, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Hitoshi Ninomiya, Yoshinao Miura
  • Publication number: 20070052015
    Abstract: Aiming at realizing high breakdown voltage and low ON resistance of a semiconductor device having the super-junction structure, the semiconductor device of the present invention has a semiconductor substrate having an element forming region having a gate electrode formed therein, and a periphery region formed around the element forming region, and having an field oxide film formed therein; and a parallel p-n layer having n-type drift regions and p-type column regions alternately arranged therein, formed along the main surface of the semiconductor substrate, as being distributed over the element forming region and a part of the periphery region, wherein the periphery region has no column region formed beneath the end portion on the element forming region side of the field oxide film and has p-type column regions as at least one column region formed under the field oxide film.
    Type: Application
    Filed: September 6, 2006
    Publication date: March 8, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yoshinao Miura, Hitoshi Ninomiya
  • Publication number: 20070029543
    Abstract: To enhance the super-junction effect of a semiconductor device having the super-junction structure and prevent lowering in the breakdown voltage, a semiconductor device described herein has a first-conductivity-type substrate having an element forming region having a gate electrode and a source electrode formed therein, and a periphery region formed around the element forming region and having an element isolating region formed therein; and a parallel p-n layer having n-type drift regions and p-type column regions alternately arranged therein, formed along the main surface of the substrate, as extending from the element forming region to the periphery region, wherein, in the periphery region, a plurality of p-type column regions are provided outwardly from the element-forming region; and the gate electrode is a trench gate buried in the substrate, being formed so as to surround the p-type column regions also in the periphery region similarly to as in the element forming region.
    Type: Application
    Filed: August 2, 2006
    Publication date: February 8, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Hitoshi Ninomiya, Yoshinao Miura
  • Publication number: 20070012998
    Abstract: A semiconductor device has a semiconductor substrate, and a parallel p-n layer provided between the main surface and the back surface of the semiconductor substrate, and first-conductivity-type drift region and second-conductivity-type partition regions alternately arranged therein, wherein in the parallel p-n layer, the second-conductivity-type partition regions are periodically formed conforming to a basic periodicity specified by a predetermined distance, and SA/S (where, SA is a sectional area per a single second-conductivity-type partition region as viewed in a plane parallel with the main surface, and S is a sectional area of a unit structural region, periodically formed as containing one of the second-conductivity-type partition regions, as viewed in a plane parallel with the main surface) in an element-forming region allowing current to flow therethrough is smaller than SA/S in at least a portion of a periphery region surrounding the element-forming region.
    Type: Application
    Filed: July 11, 2006
    Publication date: January 18, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yoshinao Miura, Hitoshi Ninomiya
  • Publication number: 20060151831
    Abstract: A semiconductor device 100 includes an element-forming region having gate electrode 108 formed therein, and a circumferential region formed in the outer circumference of the element-forming region and having an element-isolating region 118 formed therein. On the main surface of the semiconductor substrate 101, there is formed a parallel pn layer having an N-type drift region 104 and P-type column regions 106 alternately arranged therein. In the circumferential region, there is formed a field electrode 120, but the field electrode 120 is not formed on the P-type column regions 106. The P-type column regions 106 in the circumferential region are formed with a depth larger than or equal to that of the P-type column regions 106 in the element-forming region.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 13, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Hitoshi Ninomiya, Yoshinao Miura
  • Publication number: 20060124995
    Abstract: A conventional power MOSFET structure is difficult to improve a breakdown voltage of an element even using a super-junction structure. A power MOSFET according to an embodiment of the invention is a semiconductor device of a super-junction structure, including: a gate electrode filled in a trench formed on a semiconductor substrate; a gate wiring metal forming a surface layer; and a gate electrode plug connecting between the gate electrode and the gate wiring metal. Thus, a polysilicon layer necessary for the conventional typical power MOSFET is unnecessary. That is, column regions of an element active portion and an outer peripheral portion can be formed under the same conditions. As a result, it is possible to improve an element breakdown voltage as compared with the conventional one.
    Type: Application
    Filed: December 7, 2005
    Publication date: June 15, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Hitoshi Ninomiya, Yoshinao Miura
  • Publication number: 20060076614
    Abstract: A semiconductor device well balanced between high voltage applicability and low ON resistance, includes an n+-type semiconductor substrate; an n-type drift region formed thereon; a p-type base region formed on the n-type drift region; a plurality of p-type column regions in the n-type drift region so as to contact with the p-type base region and having a predetermined depth in a direction perpendicular to the p-type base region; a plurality of gate electrodes spaced by a regular distance from the centers, as viewed in the depth-wise direction, of each p-type column region, and penetrating the p-type base region, and partly buried in the n-type drift region; n-type source regions provided in the surficial region of the p-type base region around each of the gate electrodes; a drain electrode connected to the back surface of the n+-type semiconductor substrate; and a source electrode connected to the n-type source regions.
    Type: Application
    Filed: September 8, 2005
    Publication date: April 13, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Hitoshi Ninomiya
  • Publication number: 20050247957
    Abstract: A semiconductor device comprises a drift region of a first conduction type, a base region of a second conduction type, a source region of the first conduction type, a contact hole, a column region of the second conduction type, a plug and wiring. The drift region formed on a semiconductor substrate of the first conduction type. The base region of a second is formed in a prescribed region of the surface of the drift region. The source region is formed in a prescribed region of the surface of the base region. The contact hole extends from the source region surface side to the base region. The column region is formed in the drift region below the contact hole. The plug comprises a first conductive material and fills the contact hole. The wiring comprises a second conductive material and is electrically connected to the plug.
    Type: Application
    Filed: May 6, 2005
    Publication date: November 10, 2005
    Applicant: NEC Electronics Corporation
    Inventor: Hitoshi Ninomiya
  • Publication number: 20050212053
    Abstract: The present invention provides a super-junction semiconductor element having a high voltage resistance and a low resistivity, while being successfully reduced in the size thereof, which comprises a semiconductor substrate 3; a pair of electrodes 1, 2 provided respectively on a top surface 12 and a back surface 13 of the semiconductor substrate 3; a parallel pn layer provided between the top surface 12 and the back surface 13 of said semiconductor substrate, having n-type semiconductor layers 4 allowing current flow under the ON state but being depleted under the OFF state, and p-type semiconductor layers 5 alternately arranged therein; and an insulating film 6 formed so as to surround the parallel pn layer; wherein the insulating film 6 is formed at a predetermined position.
    Type: Application
    Filed: March 22, 2005
    Publication date: September 29, 2005
    Applicant: NEC Electronics Corporation
    Inventors: Yoshinao Miura, Hitoshi Ninomiya
  • Publication number: 20040245570
    Abstract: A semiconductor device includes a first conductivity type semiconductor substrate. A first conductivity type drift layer is formed on a surface of the first conductivity type semiconductor substrate, and a second conductivity type base region is produced in the first conductivity type drift layer. The second conductivity type base region has a trench formed in a surface thereof. A trench-stuffed layer is formed by stuffing the trench with a suitable material, and a second conductivity type column region formed in the first conductivity type drift layer and sited beneath the trench-stuffed layer.
    Type: Application
    Filed: April 28, 2004
    Publication date: December 9, 2004
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Hitoshi Ninomiya
  • Patent number: 6769979
    Abstract: An air cleaning system comprising an air cleaner provided on a vehicle and a device which can keep the air cleaner in operation while a vehicle is parked, whereby the quality of air inside a passenger compartment of the vehicle can be improved while the vehicle is parked. Consequently, the quality of the air can be improved in advance before an occupant enters the vehicle, and the quality of the air can further be improved without fully depending upon the function of a catalytic filter of the air cleaning system.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: August 3, 2004
    Assignee: Denso Corporation
    Inventors: Yukitaka Abe, Hitoshi Ninomiya, Motomi Mizuno, Hiroshi Kataoka, Shinji Iwama
  • Patent number: 6723146
    Abstract: A blower apparatus for a vehicle for blowing air into a cabin. The blower apparatus including a case member, various units and airflow passages. The units include an air cleaning unit for cleaning the air, and a component-adding unit for adding air components such as ions to the air. The units have compatible external shapes and sizes for selective installation in almost the same positions in the airflow passages, thereby meeting user needs of changing the function of the blower apparatus simply by arranging the units to the desired positions.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: April 20, 2004
    Assignee: Denso Corporation
    Inventors: Hitoshi Ninomiya, Yukitaka Abe, Shinji Iwama, Kazutoshi Nishizawa
  • Patent number: 6639275
    Abstract: A semiconductor device improves the gate withstand voltage of vertical MOSFETs and raises their operation speed. The gate electrode is formed in the trench of the second semiconductor layer. The interlayer dielectric layer has the contact hole that exposes the connection portion of the gate electrode, where the connection portion is located in the trench. The conductive plug is filled in the contact hole of the interlayer dielectric layer in such a way as to contact the connection portion of the gate electrode. The wiring layer is formed on the interlayer dielectric layer in such a way as to contact the plug, resulting in the wiring layer electrically connected to the connection portion by way of the plug. There is no need to form a connection portion for the gate electrode outside of the trench, which means that the gate dielectric does not include a weak or thinner portion where dielectric breakdown is likely to occur.
    Type: Grant
    Filed: June 10, 2002
    Date of Patent: October 28, 2003
    Assignee: NEC Corporaiton
    Inventor: Hitoshi Ninomiya
  • Publication number: 20030186644
    Abstract: An air cleaning system comprising an air cleaner provided on a vehicle and a device which can keep the air cleaner in operation while a vehicle is parked, whereby the quality of air inside a passenger compartment of the vehicle can be improved while the vehicle is parked. Consequently, the quality of the air can be improved in advance before an occupant enters the vehicle, and the quality of the air can further be improved without fully depending upon the function of a catalytic filter of the air cleaning system.
    Type: Application
    Filed: March 25, 2003
    Publication date: October 2, 2003
    Inventors: Yukitaka Abe, Hitoshi Ninomiya, Motomi Mizuno, Hiroshi Kataoka, Shinji Iwama