Patents by Inventor Hitoshi Okamoto

Hitoshi Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190014985
    Abstract: Provided is a light detecting apparatus comprising a light emitting section that emits light; a light detecting section that detects light from an observation target irradiated with the light emitted by the light emitting section; a mount section attached to a test subject that includes the observation target; and a holding section that holds the light emitting section and the light detecting section and is detachably attached to the mount section. The holding section holds the light emitting section and the light detecting section in a manner to secure a relative positional relationship between the light emitting section and the light detecting section, and a relative positional relationship between the holding section and the mount section is determined by attaching the holding section to the mount section.
    Type: Application
    Filed: September 3, 2018
    Publication date: January 17, 2019
    Inventors: Takuma KOBAYASHI, Hitoshi OKAMOTO, Hiroyuki IINO, Kazushige OOI
  • Patent number: 9530385
    Abstract: A display device includes: a reduction section (15) for displaying, in a case where (i) a part of a content contained in a page is visually recognizable by magnifying and displaying the page at a magnification ratio (8) and (ii) a user conducts a turn-over operation (1), an entire page to be displayed in accordance with the turn-over operation (1); and a magnification section (16) for magnifying a given part of the page at the magnification ratio (8).
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: December 27, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Ryuji Ikeda, Hitoshi Okamoto
  • Patent number: 9350880
    Abstract: There is provided an image processing apparatus. An image sequence acquisition section acquires an image sequence including a plurality of images. A sorting information acquisition section analyzes the individual images included in the image sequence, and acquires sorting information corresponding to the images on the basis of an analysis result. An image sequence generation section generates, based on the sorting information, one or a plurality of pieces of information indicating an image sequence which includes at least part of the plurality of images.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: May 24, 2016
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Tetsuya Kimura, Atsushi Hirano, Hitoshi Okamoto, Kengo Shinozaki
  • Patent number: 9158968
    Abstract: An apparatus for extracting a changed part of an image includes a separate graphic-element acquisition unit configured to acquire separate graphic-elements included in each of a first image and a second image and an integrative graphic-element acquisition unit configured to associate the separate graphic-elements with one another based on geometric relation thereamong, and to acquire integrative graphic-elements each including the separate graphic-elements associated with one another. The apparatus further includes a correspondence relation acquisition unit configured to acquire correspondence relation between the integrative graphic-element included in the first image and the integrative graphic-element included in the second image and a changed part extraction unit configured to extract a changed part between the first image and the second image based on the correspondence relation.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: October 13, 2015
    Assignee: FUJI XEROX CO., LTD.
    Inventor: Hitoshi Okamoto
  • Publication number: 20150189105
    Abstract: There is provided an image processing apparatus. An image sequence acquisition section acquires an image sequence including a plurality of images. A sorting information acquisition section analyzes the individual images included in the image sequence, and acquires sorting information corresponding to the images on the basis of an analysis result. An image sequence generation section generates, based on the sorting information, one or a plurality of pieces of information indicating an image sequence which includes at least part of the plurality of images.
    Type: Application
    Filed: March 11, 2015
    Publication date: July 2, 2015
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Tetsuya KIMURA, Atsushi HIRANO, Hitoshi OKAMOTO, Kengo SHINOZAKI
  • Publication number: 20140225932
    Abstract: A display device includes: a reduction section (15) for displaying, in a case where (i) a part of a content contained in a page is visually recognizable by magnifying and displaying the page at a magnification ratio (8) and (ii) a user conducts a turn-over operation (1), an entire page to be displayed in accordance with the turn-over operation (1); and a magnification section (16) for magnifying a given part of the page at the magnification ratio (8).
    Type: Application
    Filed: May 25, 2012
    Publication date: August 14, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Ryuji Ikeda, Hitoshi Okamoto
  • Patent number: 8804187
    Abstract: An image processing apparatus includes a composite image generator and a print controller. The composite image generator generates a composite image by superimposing, on a document image of a document represented by document data, two-dimensional code images individually corresponding to multiple document elements included in the document. The print controller causes a printer to print the composite image. The composite image generator determines positions of the two-dimensional code images corresponding to the document elements so that the positions do not overlap images of the document elements.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: August 12, 2014
    Assignee: Fuji Xerox Co.., Ltd.
    Inventors: Atsushi Hirano, Tetsuya Kimura, Hitoshi Okamoto, Kengo Shinozaki
  • Patent number: 8749932
    Abstract: A protection circuit includes a first power supply system including a first power supply and a first ground, a second power supply system including a second power supply and a second ground, and a control circuit that, when coupled to an electro-static discharge (ESD) stress being applied to the first power supply system, controls a first switch. The first switch is provided between the signal line and the first ground. The control circuit includes a capacitance element, a resistance element in series with the capacitance element, and an inverter, an output of the inverter being connected between a gate of the first switch, an input of the inverter being connected to a connecting point between the capacitance element and the resistance element.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: June 10, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Masanori Tanaka, Morihisa Hirata, Hitoshi Okamoto
  • Publication number: 20140092406
    Abstract: An image processing apparatus includes a composite image generator and a print controller. The composite image generator generates a composite image by superimposing, on a document image of a document represented by document data, two-dimensional code images individually corresponding to multiple document elements included in the document. The print controller causes a printer to print the composite image. The composite image generator determines positions of the two-dimensional code images corresponding to the document elements so that the positions do not overlap images of the document elements.
    Type: Application
    Filed: January 25, 2013
    Publication date: April 3, 2014
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Atsushi HIRANO, Tetsuya KIMURA, Hitoshi OKAMOTO, Kengo SHINOZAKI
  • Patent number: 8655107
    Abstract: An image processing apparatus includes an acquiring unit, a specifying unit, a search unit and a difference extracting unit. The acquiring unit acquires a first image and a second image. The specifying unit specifies one or more image areas included in the first image. The search unit searches the second image for an image area corresponding to each of the one or more image areas specified by the specifying unit. The difference extracting unit extracts a difference between the corresponding image area obtained by the search unit and each of the one or more image areas specified by the specifying unit.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: February 18, 2014
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Hitoshi Okamoto
  • Publication number: 20130236101
    Abstract: An information processing apparatus includes an image receiving unit receiving an image including an information image which is an image indicating information, an extraction unit extracting image identification information for identifying the image and a position in the image from the information image in the image received by the image receiving unit, a correlation unit correlating operator identification information for identifying an operator performing an operation with the image identification information and the position in the image extracted by the extraction unit, an output unit outputting a result of the correlation by the correlation unit, and a presentation unit extracting operator identification information corresponding to the image identification information and the position in the image extracted by the extraction unit from a memory which stores information output by the output unit, and presenting a symbol indicating an operator on the image on the basis of the operator identification inform
    Type: Application
    Filed: September 11, 2012
    Publication date: September 12, 2013
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Hitoshi OKAMOTO, Tetsuya KIMURA, Kengo SHINOZAKI, Akira SEKINE, Tohru HISANO, Atsushi HIRANO
  • Patent number: 8372704
    Abstract: A manufacturing method for a semiconductor integrated device including forming a second impurity layer of a second conductivity type that is higher in impurity concentration than a second well of the second conductivity type on a first impurity layer of a first conductivity type that is higher in impurity concentration than a first well of the first conductivity type, forming the first well of the first conductivity type on the second impurity layer of the second conductivity type on the first impurity layer of the first conductivity type, the first well being supplied with potential from the first impurity layer of the first conductivity type, and forming the second well of the second conductivity type on the second impurity layer of the second conductivity type on the first impurity layer of the first conductivity type, the second well being supplied with potential from the second impurity layer of the second conductivity type.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: February 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hitoshi Okamoto
  • Publication number: 20120307408
    Abstract: A protection circuit includes a first power supply system including a first power supply and a first ground, a second power supply system including a second power supply and a second ground, and a control circuit that, when coupled to an electro-static discharge (ESD) stress being applied to the first power supply system, controls a first switch. The first switch is provided between the signal line and the first ground. The control circuit includes a capacitance element, a resistance element in series with the capacitance element, and an inverter, an output of the inverter being connected between a gate of the first switch, an input of the inverter being connected to a connecting point between the capacitance element and the resistance element.
    Type: Application
    Filed: August 15, 2012
    Publication date: December 6, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Masanori TANAKA, Morihisa Hirata, Hitoshi Okamoto
  • Patent number: 8270132
    Abstract: A protection circuit that includes a first power supply system including a first power supply and a first ground, a second power supply system including a second power supply and a second ground, the second power supply system being connected to the first power supply system via a signal line through which signal transfer is performed between a circuit in the first power supply system and a circuit in the second power supply system, and a control circuit that, when coupled to an electro-static discharge (ESD) stress being applied to the first power supply system controls a switch, the switch being provided between the signal line and the first power supply.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: September 18, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Masanori Tanaka, Morihisa Hirata, Hitoshi Okamoto
  • Patent number: 8129793
    Abstract: A first exemplary aspect of an exemplary embodiment of the present invention is a semiconductor integrated device comprising a semiconductor substrate, a first impurity layer of a first conductivity type formed in the semiconductor substrate, a second impurity layer of a second conductivity type formed on the first impurity layer, a first well of the first conductivity type formed on the second impurity layer and supplied with potential from the first impurity layer via an impurity region of the first conductivity type selectively formed in a part of the second impurity layer, and a second well of the second conductivity type formed on the second impurity layer and supplied with potential from the second impurity layer, wherein the impurity concentrations of the first impurity layer and the impurity region are higher than that of the first well, and the impurity concentration of the second impurity layer is higher than that of the second well.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: March 6, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hitoshi Okamoto
  • Publication number: 20120044257
    Abstract: An apparatus for extracting a changed part of an image includes a separate graphic-element acquisition unit configured to acquire separate graphic-elements included in each of a first image and a second image and an integrative graphic-element acquisition unit configured to associate the separate graphic-elements with one another based on geometric relation thereamong, and to acquire integrative graphic-elements each including the separate graphic-elements associated with one another. The apparatus further includes a correspondence relation acquisition unit configured to acquire correspondence relation between the integrative graphic-element included in the first image and the integrative graphic-element included in the second image and a changed part extraction unit configured to extract a changed part between the first image and the second image based on the correspondence relation.
    Type: Application
    Filed: May 10, 2011
    Publication date: February 23, 2012
    Applicant: FUJI XEROX CO., LTD.
    Inventor: Hitoshi OKAMOTO
  • Patent number: 8009315
    Abstract: An information management apparatus comprises: an assignment unit that uniquely assigns a region on an imaginary plane for a page of a document that is output by an image forming apparatus; a receiving unit that receives a request for assignment by the assignment unit, and identification information that identifies the document; a notification unit that notifies the image forming apparatus of coordinate values in a region assigned by the assignment unit, as coordinate values expressed on the document image of the page using a predetermined code; a storage unit that stores, for each region assigned by the assignment unit, region information that indicates the region and the identification information, the region information and the identification information being stored associated with each other; and a search unit that, when a coordinate value is input, searches for the identification information associated with the region that includes the coordinate value in the storage unit.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: August 30, 2011
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Hitoshi Okamoto
  • Patent number: 8008727
    Abstract: To reduce the leak current in the MOSFET connected between the pad and the ground. There are provided a pad PAD for an input or output signal, an n-type MOSFET M1a connected between the pad PAD and the ground and having its gate terminal and backgate connected in common, and a potential control circuit 10 that controls a potential Vb of the gate terminal and the backgate of the n-type MOSFET M1a based on a potential Vin of the pad PAD. The potential control circuit 10 comprises n-type MOSFETs M2 and M3; the n-type MOSFET M1a has its gate terminal and backgate connected to backgates and drains of the n-type MOSFETs M2 and M3; the n-type MOSFET M2 has its source grounded and its gate terminal connected to the pad PAD via a resistance R; and the n-type MOSFET M3 has its source connected to the pad PAD and its gate terminal grounded.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: August 30, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hitoshi Okamoto, Morihisa Hirata
  • Publication number: 20110143523
    Abstract: A manufacturing method for a semiconductor integrated device including forming a second impurity layer of a second conductivity type that is higher in impurity concentration than a second well of the second conductivity type on a first impurity layer of a first conductivity type that is higher in impurity concentration than a first well of the first conductivity type, forming the first well of the first conductivity type on the second impurity layer of the second conductivity type on the first impurity layer of the first conductivity type, the first well being supplied with potential from the first impurity layer of the first conductivity type, and forming the second well of the second conductivity type on the second impurity layer of the second conductivity type on the first impurity layer of the first conductivity type, the second well being supplied with potential from the second impurity layer of the second conductivity type.
    Type: Application
    Filed: February 22, 2011
    Publication date: June 16, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Hitoshi Okamoto
  • Publication number: 20110102962
    Abstract: A protection circuit that includes a first power supply system including a first power supply and a first ground, a second power supply system including a second power supply and a second ground, the second power supply system being connected to the first power supply system via a signal line through which signal transfer is performed between a circuit in the first power supply system and a circuit in the second power supply system, and a control circuit that, when coupled to an electro-static discharge (ESD) stress being applied to the first power supply system controls a switch, the switch being provided between the signal line and the first power supply.
    Type: Application
    Filed: January 7, 2011
    Publication date: May 5, 2011
    Applicant: Renesas Electronics Corporation
    Inventors: Masanori Tanaka, Morihisa Hirata, Hitoshi Okamoto