Patents by Inventor Hitoshi Omichi

Hitoshi Omichi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4868630
    Abstract: A semiconductor integrated circuit including at least one conventional inner cell region and an outer cell region. The outer cell region comprising a plurality of outer cells. Each outer cell is comprised of circuit elements for achieving a predetermined logic function, in addition to circuit elements for achieving the conventional buffer function of an outer cell. Further, two or more adjacent outer cells are connected each other and act as an independent circuit so as to form a macro-cell.
    Type: Grant
    Filed: August 27, 1985
    Date of Patent: September 19, 1989
    Assignee: Fujitsu Limited
    Inventors: Tetsu Tanizawa, Yoshiharu Mitono, Hitoshi Omichi
  • Patent number: 4564773
    Abstract: In a semiconductor device having a gate array structure, a macro-cell includes more basic cells than conventional macro-cells, for preforming a logic function, whereby the density of the terminals in a direction vertical to a direction in which wiring lines are drawn, is decreased.
    Type: Grant
    Filed: August 11, 1982
    Date of Patent: January 14, 1986
    Assignee: Fujitsu Limited
    Inventors: Tetsu Tanizawa, Hitoshi Omichi, Yoshiharu Mitono
  • Patent number: 4523106
    Abstract: An integrated circuit device such as a gate array or a master slice LSI device which is formed on a semiconductor chip and which comprises an inner cell array including a plurality of inner cells, an outer cell array including a plurality of outer cells formed around the inner cell array, a power supply portion having one or more outer power supply lines, and a plurality of inner power supply lines connected to the outer power supply lines and formed on the inner cell array. The ratio of the pitch length of the outer cells to the pitch length of the inner power supply lines or the inner cells is determined by the ratio of two integers. In the integrated circuit device, at least one set of an outer cell, and an inner cell which are arranged in a predetermined positional relation, is formed a plurality of times along a side of the semiconductor chip.
    Type: Grant
    Filed: August 25, 1982
    Date of Patent: June 11, 1985
    Assignee: Fujitsu Limited
    Inventors: Tetsu Tanizawa, Hitoshi Omichi, Yoshiharu Mitono
  • Patent number: 4499484
    Abstract: In an integrated circuit manufactured by the master slice method, the feeder line for supplying electric power to a unit-cell array is gradually narrowed in width from the periphery to the middle of the array. As a result, sufficient voltage is supplied to the unit-cells at the middle of the IC and an area of an interconnecting domain for connecting the unit-cells is expanded.
    Type: Grant
    Filed: September 8, 1982
    Date of Patent: February 12, 1985
    Assignee: Fujitsu Limited
    Inventors: Tetsu Tanizawa, Hitoshi Omichi, Yoshiharu Mitono