Hizuru Nawata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A unique word detection apparatus for detecting a unique word out of a demodulated signal resulting from the demodulation of a burst signal consisting of a carrier recovery section, a bit timing recovery section, a unique word section and a data section. The magnitude of the D.C. component of the demodulated signal is extracted, and the timing of the transition of this D.C. component from large to small is detected. An aperture signal designating the period in which to detect the unique word on the basis of the transition timing of the D.C. component generated, and the unique word out of the demodulated signal entered during the period designated by the aperture signal is accurately detected.
Abstract: In a burst demodulator, an APSK burst signal containing a preamble of alternating "1" and "-1" symbols, followed by a data field is received and quasi-coherently demodualted into a baseband complex signal, which is converted to digital form such that each symbol of the complex signal yields N digital samples, with N being selected such that at least one of the N digital samples is closest to a signal point of the burst signal. A clock recovery circuit is responsive to the arrival of the burst for estimating the symbol timing of the burst signal from digital samples of the preamble. A digital sample is extracted from every N samples of the preamble in response to the estimated symbol timing so that it is most likely to be closest to the signal point.
Abstract: In a satellite communications system, a time slot assignment signal and a reference timing signal are transmitted from a central station to terminal stations to allow them to send bursts on assigned time slots and to establish the frame timing. In the central station, first and second self-resettable counters increment their respective binary counts at clock intervals and reset their counts to an initial value at time-slot intervals. A local timing signal is generated synchronously with the reference timing signal and delayed by an amount corresponding to a minimum round-trip propagation delay to reset the first counter. In an initial, wide aperture mode, the output of the first counter is used to generate control signals for recovering a carrier and clock and widely opening an aperture gate for detecting unique words of a burst that is affected by satellite drift.
Abstract: An automatic gain control (AGC) for a demodulator which receives digitally modulated burst signals time-serially from a plurality of terminals. The AGC has a series connection of a variable attenuator and a limiter that precedes a demodulator. The variable attenuator is controlled such that when a burst signal is absent, the noise power level inputted to the limiter coincides with a predetermined reference value, whereby when burst signal is present, the limiter controls the burst signal to a predetermined level. As a result, when burst signals greatly differ in level from one another, they are controlled to the predetermined level in their preamble word portions. This insures stable demodulation of data signals.
Abstract: In a satellite communication system wherein a common channel is used for communication between a central station (10) and a plurality of remote stations (12) through a satellite transponder (11), in order to avoid system down due to fault of transmission of a broadcasting signal with a timing signal by the central station (10), the central station (10) comprises two portions (13, 14) positioned at different locations and a controller (15). When the first portion (13) detects fault of transmission of the broadcasting signal during the first portion (13) operates to communicate with the remote stations (12) under transmission of the broadcasting signal, the controller (15) is notified the fault and starts the second portion (14) in place of the first portion (13) so that the communication is maintained in the system without false. Those portions (13, 14) are assigned with ID numbers and can detect the fault by detecting operation of ID number.
Abstract: A phase comparator included in a phase locked loop (PLL) for comparing two input signals with respect to phase to thereby determine their phase difference includes two multipliers and two low-pass filters for producing a sine component signal and a cosine component signal which are associated with the phase difference. A discrimination signal representative of a polarity is generated on the basis of one of those two component signals, and a phase error signal is generated on the basis of the other of them. The phase error signal monotonously increases during predetermined one period which is determined by the discrimination signal, i.e. (2n-1).pi. to (2n+1).pi. where n is 0, .+-.1, .+-.2 and so on. A PLL using such a phase comparator is allowed to rapidly converge to a stable point even when the phase error is close to an unstable point, i.e., .+-.(2n-1) where n is 0, 1, 2 and so on, achieving an extremely short acquisition time.
Abstract: A carrier recovery circuit comprises a voltage-controlled oscillator with a .pi./2 phase shifter coupled to it for generating carriers of quadrature phase relationship. First and second phase comparators respectively detect phase differences between an offset QPSK modulated signal and the carriers of the quadrature phase relationship. Signal from the first phase comparator is delayed by a 1/2 symbol duration and applied to one input of a quadri-phase detector having stable phase angles at .pi./4, (3/4).pi., (5/4).pi. and (7/4).pi. radian and signal from the second phase comparator is applied to the other input of the quadri-phase detector. A bit timing recovery field (1010 . . . 1010) of the second channel is detected from the output of the second phase comparator. Signal from the quadri-phase detector is applied to a loop filter and thence to the voltage-controlled oscillator during the time when a bit timing recovery field (BTR) of the second channel is not still detected.
Abstract: A phase detecting circuit for detecting a phase differential between a reference clock and a bit timing extracted from a demodulated signal, which is derived from a modulation wave modulated by a digital signal. The circuit successfully eliminates points of discontinuity in the phase detection characteristic of a phase detector and, therefore, accurately determines a phase differential between the bit timing and the reference clock with no regard to the magnitude of the phase differential of an input. An absolute value averaging circuit is provided for averaging the absolute valves of a plurality of consecutive outputs of a phase detector. A sign majority decision circuit is provided for producing one of positive and negative signs of the consecutive outputs of the phase detector which is decided by majority.