Abstract: A heterogeneous integration capacitor and a metal-oxide-metal (MoM) capacitor are provided. The heterogeneous integration capacitor has a first electrode and a second electrode, and includes a substrate, a semiconductor capacitor, the MoM capacitor, and a metal-insulator-metal (MiM) capacitor. These capacitors are sequentially formed on the substrate, and are formed as connected in parallel.

Abstract: A technique for displaying 3D videos creates a representation of image deformation, such as depth maps, in terms of a function for overlaying kernels with variable support and order. By optimizing the kernel type, order and support, which are allowed to be varied across different region of the deformation, it is able to approximate the image deformations in terms of the kernel parameters. Since the number of kernel parameters is usually much smaller than that of the number of pixels, this allows a significant reduction in the storage size of the image deformation.

Abstract: A technique for displaying 3D videos creates a representation of image deformation, such as depth maps, in terms of a function for overlaying kernels with variable support and order. By optimizing the kernel type, order and support, which are allowed to be varied across different region of the deformation, it is able to approximate the image deformations in terms of the kernel parameters. Since the number of kernel parameters is usually much smaller than that of the number of pixels, this allows a significant reduction in the storage size of the image deformation.

Abstract: The present invention relates to a logic circuit comprising a first and a second circuits coupled in series between two voltage levels, wherein the first circuit includes a plurality of first transistors coupled in parallel and each adapted to receive an input signal; the second circuit includes a plurality of transistor sets each including a plurality of second transistors, the second transistors are coupled in series and to one of the input signals, and the second transistors of each transistor set couples to the input signals in a manner different from that of each of the remaining transistor sets. By utilizing this logic circuit, to all of the input signals, the second circuit operates with the same time delay.

Abstract: An Schmitt trigger with electrostatic discharge protection includes a first PMOS, a second PMOS, a first NMOS, and a second NMOS, which are connected in series and each of which has a gate coupled to an input terminal. The drain of the second PMOS is coupled to an output terminal. The source of the first PMOS is coupled to a first voltage. The source of the second NMOS is coupled to a second voltage. The Schmitt trigger further includes a third PMOS, which has a gate coupled to the output terminal, a source coupled to the drain of the first PMOS, and a drain coupled to the second voltage through a poly-silicon resistor; and a third NMOS which has a gate coupled to the output terminal, a source coupled to the source of the first NMOS, and a drain coupled to the first voltage through a poly-silicon resistor.