Patents by Inventor Ho-Shing LEE

Ho-Shing LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220157687
    Abstract: A circuit substrate has an open substrate, a heat-dissipation block, multiple high thermal conductivity members, a first dielectric layer, a second dielectric layer, multiple first heat conductive members, and multiple second heat conductive members. The heat-dissipation block is disposed in the open substrate. Multiple high thermal conductivity members are mounted through the heat-dissipation block. The first dielectric layer exposes a part of one of two surfaces of the heat-dissipation block. The second dielectric layer exposes a part of the other surface of the heat-dissipation block. The first heat conductive members are in contact with the heat-dissipation block exposed from the first dielectric layer. The second heat conductive members are in contact with the part of the heat-dissipation block exposed from the second dielectric layer.
    Type: Application
    Filed: January 25, 2021
    Publication date: May 19, 2022
    Inventors: Chien-Chen LIN, Ho-Shing LEE
  • Patent number: 11153963
    Abstract: A circuit carrier structure includes an inner circuit structure, at least one first circuit layer, and at least one heat dissipating structure. The inner circuit structure has a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface of the inner circuit structure. The heat dissipating structure is disposed in the first circuit layer. The heat dissipating structure includes a first heat dissipating pattern, a second heat dissipating pattern and an interlayer metal layer. The first heat dissipating pattern is embedded in the corresponding first circuit layer. The second heat dissipating pattern is disposed on the first heat dissipating pattern. The interlayer metal layer is disposed between the first heat dissipating pattern and the second heat dissipating pattern. A manufacturing method of the circuit carrier structure is also provided.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: October 19, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Chang-Fu Chen, Ho-Shing Lee, Chien-Chen Lin
  • Publication number: 20210289614
    Abstract: A circuit carrier structure includes an inner circuit structure, at least one first circuit layer, and at least one heat dissipating structure. The inner circuit structure has a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface of the inner circuit structure. The heat dissipating structure is disposed in the first circuit layer. The heat dissipating structure includes a first heat dissipating pattern, a second heat dissipating pattern and an interlayer metal layer. The first heat dissipating pattern is embedded in the corresponding first circuit layer. The second heat dissipating pattern is disposed on the first heat dissipating pattern. The interlayer metal layer is disposed between the first heat dissipating pattern and the second heat dissipating pattern. A manufacturing method of the circuit carrier structure is also provided.
    Type: Application
    Filed: April 10, 2020
    Publication date: September 16, 2021
    Applicant: Unimicron Technology Corp.
    Inventors: Chang-Fu Chen, Ho-Shing Lee, Chien-Chen Lin
  • Patent number: 10856421
    Abstract: A circuit board is disposed on a substrate and includes a dielectric layer and a circuit layer. The dielectric layer is disposed on the substrate. The circuit layer is embedded in the dielectric layer and has plural traces. Each of the traces has a first top surface and a first bottom surface which are opposite to each other, and the first bottom surface faces toward the substrate. The first top surface is exposed from the dielectric layer, and an area of a vertical projection of the first top surface on the substrate is smaller than an area of a vertical projection of the first bottom surface on the substrate.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: December 1, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Ching-Hao Huang, Ho-Shing Lee, Yu-Cheng Lin
  • Publication number: 20200077521
    Abstract: A circuit board is disposed on a substrate and includes a dielectric layer and a circuit layer. The dielectric layer is disposed on the substrate. The circuit layer is embedded in the dielectric layer and has plural traces. Each of the traces has a first top surface and a first bottom surface which are opposite to each other, and the first bottom surface faces toward the substrate. The first top surface is exposed from the dielectric layer, and an area of a vertical projection of the first top surface on the substrate is smaller than an area of a vertical projection of the first bottom surface on the substrate.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 5, 2020
    Inventors: Ching-Hao HUANG, Ho-Shing LEE, Yu-Cheng LIN
  • Patent number: 10512165
    Abstract: A circuit board is disposed on a substrate and includes a dielectric layer and a circuit layer. The dielectric layer is disposed on the substrate. The circuit layer is embedded in the dielectric layer and has plural traces. Each of the traces has a first top surface and a first bottom surface which are opposite to each other, and the first bottom surface faces toward the substrate. The first top surface is exposed from the dielectric layer, and an area of a vertical projection of the first top surface on the substrate is smaller than an area of a vertical projection of the first bottom surface on the substrate.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: December 17, 2019
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Ching-Hao Huang, Ho-Shing Lee, Yu-Cheng Lin
  • Publication number: 20180279480
    Abstract: A circuit board is disposed on a substrate and includes a dielectric layer and a circuit layer. The dielectric layer is disposed on the substrate. The circuit layer is embedded in the dielectric layer and has plural traces. Each of the traces has a first top surface and a first bottom surface which are opposite to each other, and the first bottom surface faces toward the substrate. The first top surface is exposed from the dielectric layer, and an area of a vertical projection of the first top surface on the substrate is smaller than an area of a vertical projection of the first bottom surface on the substrate.
    Type: Application
    Filed: March 23, 2017
    Publication date: September 27, 2018
    Inventors: Ching-Hao HUANG, Ho-Shing LEE, Yu-Cheng LIN